My Inquiry
My Account
Microchip Technology PM40036B1-F3EI
- Part No.:
- PM40036B1-F3EI
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- -
- Datasheet:
-
PM40036B1-F3EI.pdf
- Description:
- IC PFX 36XG4, 36-LANE PCIE SWITC
- Quantity:
- Payment:
- Shipping:
Inventory:2,737
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PM40036B1-F3EI from Microchip Technology is a PCIe Gen 4 fanout switch IC with 36 lanes, 20 ports (18 NTBs), 10 virtual switch partitions, and hot-plug controllers on all 20 ports. It integrates a MIPS processor, supports x1/x2/x4/x8/x16 port bifurcation, and delivers end-to-end data integrity for high-reliability server interconnects.
For engineers reviewing the PM40036B1-F3EI datasheet, PM40036B1-F3EI pinout, PM40036B1-F3EI application, or PM40036B1-F3EI equivalent, key selection criteria include lane count, NTB assignment flexibility, DPC/AER error containment, real-time eye capture capability, and SGPIO/TWI peripheral I/O support for system management.
Technical Context
The PM40036B1-F3EI implements a non-blocking PCIe Gen 4 switch fabric operating at 16 GT/s with full link training compliance and manual PHY configuration support-including for optical interfaces. Its architecture enables unrestricted upstream/downstream port mapping and dynamic NTB assignment across all 20 ports.
It embeds an integrated MIPS processor for firmware execution, supports Completion Timeout Synthesis to prevent upstream host lockup, and provides Downstream Port Containment (DPC) and Advanced Error Reporting (AER) on every downstream port-critical for fault-isolated data center topologies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PCIe Generation | Gen 4 (16 GT/s) with full link training and manual PHY configuration support |
| Lane Count | 36 total high-speed serial lanes for flexible topology distribution |
| Port Count / NTBs | 20 configurable ports; up to 18 assignable non-transparent bridges |
| Virtual Partitions | 10 independent virtual switch partitions for resource isolation |
| Error Containment | DPC and AER implemented on all downstream ports; CTS prevents upstream timeout lockup |
| Peripheral Interfaces | Up to 11 TWI/SMBus ports + 4 SGPIO ports + JTAG/EJTAG debug interface |
| Hot-Plug Support | Dedicated hot- and surprise-plug controllers on all 20 ports |
Pinout & Package
PM40036B1-F3EI is housed in a 27 mm × 27 mm, 780-pin FC-BGA package with edge-aligned signal balls optimized for PCIe Gen 4 signal integrity and thermal dissipation in dense server PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLK_IN0/1 | PCIe reference clock input pair | Differential 100 MHz clock source for Gen 4 link initialization and timing recovery |
| PERST# | Global reset control | Active-low asynchronous reset that initializes switch configuration and clears internal state |
| PRSNT#_0–19 | Presence detect per port | Indicates physical connector insertion status for hot-plug event detection on each of 20 ports |
| SGPIO_CLK/DAT/ALERT | Serial GPIO bus interface | 4-wire SFF-8485-compliant bus for LED/status control and slot management |
| TWI_SCL/SDA_0–10 | Two-Wire Interface signals | Up to 11 SMBus-compatible buses for temperature sensors, EEPROMs, and PMIC communication |
Key Features
| Feature | Design Value |
|---|---|
| Real-time eye capture | On-die SERDES diagnostic capability enabling live PCIe signal integrity analysis without external equipment |
| Flexible port bifurcation | Any port configurable as x1/x2/x4/x8/x16 without upstream/downstream restrictions or lane-sharing conflicts |
| Non-transparent bridging (NTB) | 18 NTBs support peer-to-peer memory-mapped DMA between isolated domains-essential for secure multi-tenant systems |
| Boot image authentication | Hardware-enforced cryptographic verification of firmware images to prevent unauthorized or corrupted boot code execution |
| Comprehensive loopback modes | Per-port electrical, digital, and protocol-level loopbacks for deterministic bring-up and field diagnostics |
Applications
| Data Center Server Interconnect | Defense-Grade Rugged Computing |
|---|---|
Use Scenario: Fanout from a single CPU PCIe root port to multiple NVMe SSDs, GPUs, and SmartNICs in a 1U rack server. IC Role / Device Role / Timing Role: PCIe Gen 4 switch providing low-latency, non-blocking interconnect with DPC-enabled fault isolation between endpoints. Use Value: Enables 20-device connectivity with 36 lanes while maintaining per-port hot-plug and AER-reducing system downtime during maintenance. | Use Scenario: High-availability mission computer in airborne or ground vehicle platforms requiring EMI-hardened, long-lifecycle interconnect. IC Role / Device Role / Timing Role: Trusted PCIe fanout switch with authenticated boot and NTB-based domain separation for safety-critical subsystems. Use Value: Provides deterministic failover (1+1/N+1), real-time eye monitoring, and SGPIO-managed status reporting under extended temperature and vibration stress. |
| Video Production Switching Fabric | 5G Radio Unit (RU) Baseband Processing |
Use Scenario: Aggregating multiple 4K/8K video capture cards, frame synchronizers, and hardware encoders into a unified media processing chassis. IC Role / Device Role / Timing Role: Low-jitter, high-bandwidth PCIe Gen 4 switch supporting x16 GPU and x4 capture card links with precise timing synchronization. Use Value: Delivers stable 16 GT/s throughput across 20 ports with real-time eye capture-ensuring pixel-perfect video pipeline integrity. | Use Scenario: Interconnecting FPGA-based baseband processors, RF front-end controllers, and fronthaul transport interfaces in Open RAN radio units. IC Role / Device Role / Timing Role: Deterministic PCIe switch with NTB support for FPGA-to-FPGA memory sharing and JTAG-accessible debug visibility. Use Value: Enables 18 NTB-assisted DMA channels between distributed processing blocks while supporting SFF-8643 cable connectivity for compact RU form factors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PCIe fanout switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PM40036B-F3EI | Same core silicon; differs only in BGA ball map and thermal pad configuration-identical functionality and register set | No functional difference; validated for identical use cases including data center and defense servers | Select PM40036B1-F3EI when board layout requires updated mechanical footprint or enhanced thermal performance per Microchip's revision guidance |
| PM40052B-F3EI | Higher lane count (52 vs. 36), more ports (28 vs. 20), and additional NTBs (26 vs. 18); same PFX Gen 4 architecture and firmware compatibility | Suitable for larger-scale fanout where >20 endpoints or >36 lanes are required-e.g., dual-CPU server backplanes | Choose PM40052B-F3EI only if design requires ≥28 ports or ≥52 lanes; otherwise PM40036B1-F3EI offers optimal cost and power efficiency |
Compared with PM40036B-F3EI, the PM40036B1-F3EI offers identical switching functionality with refined thermal and mechanical implementation, while PM40052B-F3EI scales lane/port capacity at higher power and board area cost-making PM40036B1-F3EI the optimal choice for space-constrained 20-port PCIe Gen 4 fanout designs.
Availability
PM40036B1-F3EI is available at Aetrix Electronics and suitable for data center servers, defense computing platforms, broadcast video infrastructure, and 5G radio unit designs requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for PM40036B1-F3EI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a U.S.-based semiconductor company specializing in microcontrollers, analog devices, FPGAs, and connectivity solutions with emphasis on reliability, security, and long-life support.
The Switchtec PFX Gen 4 family-including PM40036B1-F3EI-is engineered for high-availability PCIe interconnect in mission-critical infrastructure where error containment, hot-plug resilience, and deterministic diagnostics are mandatory.
FAQ
What is the maximum number of non-transparent bridges supported by PM40036B1-F3EI?
The PM40036B1-F3EI supports up to 18 non-transparent bridges (NTBs), assignable to any of its 20 ports. This enables secure, memory-mapped peer-to-peer DMA between isolated processing domains-critical for multi-tenant data center and defense applications. The NTB count is fixed per this variant and confirmed in Microchip's official ordering table and datasheet DS00002866D.
Does PM40036B1-F3EI support PCIe Gen 4 link training and manual PHY configuration?
Yes, PM40036B1-F3EI fully supports PCIe Gen 4 link training per specification and allows manual PHY configuration-including for optical interfaces. This capability is documented in the Switchtec PFX Gen 4 Family datasheet and enables precise signal integrity tuning in high-density or electrically challenging board environments where auto-negotiation may be insufficient.
How does PM40036B1-F3EI implement error containment for downstream ports?
PM40036B1-F3EI implements Downstream Port Containment (DPC) and Advanced Error Reporting (AER) on all downstream ports. DPC isolates errors to prevent propagation to upstream hosts, while AER logs detailed error types and locations. These features are hardware-enforced and active by default-no firmware enablement required-and are verified in Microchip's PFX debug tools and errata documentation.
What peripheral interfaces are integrated into PM40036B1-F3EI?
PM40036B1-F3EI integrates up to 11 Two-Wire Interfaces (TWI/SMBus), 4 SGPIO ports compliant with SFF-8485, JTAG and EJTAG debug interfaces, and a dedicated 10/100 Ethernet MAC (MII/RMII) port. These peripherals support system management, LED control, sensor monitoring, and firmware debugging-enabling comprehensive platform-level control without external companion ICs.
Is PM40036B1-F3EI pin-compatible with other PFX Gen 4 variants like PM40052B-F3EI?
No, PM40036B1-F3EI is not pin-compatible with PM40052B-F3EI or other PFX Gen 4 variants. Each variant uses a unique FC-BGA package with distinct ball maps, lane assignments, and power delivery configurations. Board-level redesign is required when migrating between lane-count variants-even within the same PFX Gen 4 family-as confirmed in Microchip's packaging and layout guidelines.
PM40036B1-F3EI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- -
- Interface:
- -
- Voltage - Supply:
- -
- Supplier Device Package:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
PM40036B1-F3EI FAQ
1.How can I place an order for PM40036B1-F3EI through Aetrix?
Please submit a Request for Quotation (RFQ) for PM40036B1-F3EI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PM40036B1-F3EI reliable?
The price and inventory of PM40036B1-F3EI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PM40036B1-F3EI is usually 5 days.
3.What payment methods are accepted for PM40036B1-F3EI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PM40036B1-F3EI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PM40036B1-F3EI?
PM40036B1-F3EI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PM40036B1-F3EI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PM40036B1-F3EI?
For technical support, including PM40036B1-F3EI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PM40036B1-F3EI requirements.
6.How does Aetrix verify that PM40036B1-F3EI is sourced from the original manufacturer or authorized distributors?
All PM40036B1-F3EI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PM40036B1-F3EI meets industry standards.
7.What is the process for return or replacement of PM40036B1-F3EI?
All PM40036B1-F3EI units undergo pre-shipment inspection (PSI). If there is an issue with PM40036B1-F3EI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PM40036B1-F3EI part is unused and in its original packaging.
Return procedure for PM40036B1-F3EI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PM40036B1-F3EI Tags
-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments
-
MD0100N8-G
Microchip Technology
-
PCA9548APW,118
NXP Semiconductors
-
PCA9540BDP,118
NXP Semiconductors
-
PCA9548APWR
Texas Instruments
-
PCA9546APW,118
NXP Semiconductors
-
PTN3360DBS,518
NXP Semiconductors
-
PCA9546ABS,118
NXP Semiconductors
-
PCA9518PWR
Texas Instruments
-
PCA9545APW,118
NXP Semiconductors
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
