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Microchip Technology PM41036B-F3EI
- Part No.:
- PM41036B-F3EI
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- 753-BBGA
- Datasheet:
-
PM41036B-F3EI.pdf
- Description:
- PCIE SWITCH GEN4 BBGA
- Quantity:
- Payment:
- Shipping:
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Product details
Overview
PM41036B-F3EI from Microchip Technology is a Gen4 programmable PCIe switch with 36 lanes, 20 ports (18 NTBs), 10 virtual switch partitions, and dedicated hot-plug controllers per port-designed for high-reliability NVMe SSD enclosures and pooled storage systems.
For engineers reviewing the PM41036B-F3EI datasheet, PM41036B-F3EI pinout, PM41036B-F3EI application, or PM41036B-F3EI equivalent, key selection criteria include lane count scalability, NTB assignment flexibility, upstream error containment (UEC), real-time eye capture capability, and NVMe-MI in-band/out-of-band management support.
Technical Context
The PM41036B-F3EI implements a non-blocking PCIe Gen4 16 GT/s switching fabric with full support for x1/x2/x4/x8/x16 port bifurcation and configurable upstream/downstream port mapping. It integrates a MIPS processor for enclosure management firmware execution and supports both SES-based and native NVMe-MI stack for in-band management.
Each of its 20 ports includes dedicated hot- and surprise-plug controllers, Downstream Port Containment (DPC), Completion Timeout Synthesis (CTS), and programmable Upstream Error Containment (UEC). The device also provides 4 SGPIO ports, up to 11 TWIs with SMBus, and MII/RMII Ethernet MAC (in PSX 100x/84x/68xG4 variants-excluded in PM41036B-F3EI per ordering table).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Lane Count | 36 PCIe Gen4 lanes - enables flexible topology scaling without oversubscription in mid-density storage enclosures. |
| Port Count / NTBs | 20 physical ports, 18 assignable Non-Transparent Bridges - supports multi-host interconnect and isolated memory-mapped I/O across heterogeneous systems. |
| Virtual Partitions | 10 independent virtual switch partitions - allows secure resource isolation and concurrent firmware updates per partition. |
| Hot-Plug Controllers | 20 dedicated controllers (one per port) - enables safe insertion/removal of NVMe drives without host reboot or PCIe link reset propagation. |
| Error Containment | UEC, DPC, CTS, and AER on all ports - prevents error propagation to upstream hosts and maintains system uptime during device-level faults. |
| Management Interfaces | In-band NVMe-MI (SES + native stack) + out-of-band MCTP over I²C - delivers dual-path enclosure monitoring and control without requiring separate management NICs. |
| Peripheral I/O | Up to 11 TWI/SMBus, 4 SGPIO, 4 UARTs, JTAG/EJTAG - supports LED/status signaling, fan control, temperature monitoring, and debug access in dense rack-mounted systems. |
Pinout & Package
PM41036B-F3EI is housed in a 27 mm × 27 mm, 780-pin FCBGA package (package code F3EI per Microchip ordering guide). Pinout is defined in Microchip DS00003308B, Section 3.1 "Signal Descriptions" and Figure 3-1 "Ball Map". Key functional groups include PCIe RX/TX differential pairs (lanes 0–35), VDD/VSS power balls, reference clocks (REFCLK±), SMBus (SCL/SDA), SGPIO (SCLOCK/SDATA), UART (TX/RX), JTAG (TCK/TMS/TDO/TDI/TRST#), and GPIOs configured for cable detection or LED control.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PCIe_TX[35:0], PCIe_RX[35:0] | Differential high-speed serial I/O | 36 bidirectional Gen4 lanes supporting x1/x2/x4/x8/x16 bifurcation; each pair requires controlled impedance routing and AC coupling. |
| REFCLK0_P/N, REFCLK1_P/N | Differential reference clock inputs | Two independent 100 MHz differential reference clocks for lane groups; essential for link training stability and jitter compliance. |
| SMBCLK, SMBDAT | Two-Wire Interface bus | Shared SMBus interface for configuration EEPROM, temperature sensors, and hot-swap controllers; supports multi-drop topology. |
| SGPIO_SCLOCK, SGPIO_SDATA | Serial GPIO bus | Drives LED status indicators per slot/port; synchronized with drive presence and activity signals in NVMe enclosures. |
| UART0_TX, UART0_RX | Asynchronous serial debug interface | Provides low-speed console access for boot log inspection, firmware recovery, and runtime diagnostics without PCIe enumeration dependency. |
| TCK, TMS, TDO, TDI, TRST# | JTAG boundary-scan interface | Enables IEEE 1149.1-compliant testing, silicon validation, and in-circuit programming of internal configuration registers. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable Virtual Switch Partitions | 10 isolated partitions allow independent firmware loading, security policy enforcement, and failure domain containment in multi-tenant storage systems. |
| Per-Port Hot- and Surprise-Plug Controllers | 20 independent controllers eliminate need for external PLD/FPGA logic, reduce BOM cost, and ensure deterministic plug/unplug timing per NVMe slot. |
| Upstream Error Containment (UEC) | Configurable UEC blocks error propagation to root complex, enabling continued operation of unaffected host CPUs during downstream device errors. |
| NVMe-MI Management Stack | Native in-band support for NVMe enclosure services (SES) and out-of-band MCTP over I²C enables unified firmware update and health telemetry without dedicated management processors. |
| Real-Time Eye Capture | On-die SERDES eye diagram acquisition allows signal integrity validation at system level without external test equipment during bring-up and field diagnostics. |
Applications
| PCIe SSD Enclosure Management | Multi-Host NVMe Fabric |
|---|---|
Use Scenario: 2U/4U rack-mount NVMe JBOD with 24–48 hot-swappable U.2/U.3 drives managed via single enclosure controller. IC Role / Device Role / Timing Role: PCIe switch and embedded management processor handling drive enumeration, thermal/fault telemetry, LED control, and SES command routing. Use Value: Eliminates external microcontroller by integrating NVMe-MI stack, SGPIO, SMBus, and UART-reducing latency and component count in space-constrained enclosures. | Use Scenario: Two independent servers sharing a common pool of NVMe SSDs through transparent PCIe tunneling. IC Role / Device Role / Timing Role: Non-transparent bridge (NTB) interconnect enabling peer-to-peer memory access and DMA-coherent data movement between hosts. Use Value: 18 assignable NTBs allow simultaneous multi-host mappings without performance penalty, supporting dynamic resource allocation in composable infrastructure. |
| High-Density Blade Server I/O Aggregation | Enterprise Storage Controller Front-End |
Use Scenario: Blade chassis with 8–12 compute blades connecting to shared backplane storage via modular midplane switches. IC Role / Device Role / Timing Role: Scalable PCIe Gen4 fabric aggregator providing lane consolidation, port bifurcation, and error-isolated communication paths per blade slot. Use Value: 36-lane capacity and x1/x2/x4/x8/x16 flexibility enable optimal lane allocation per blade type (GPU, CPU, accelerator), maximizing backplane utilization. | Use Scenario: Dual-controller RAID/NVMe storage array where front-end switch handles host interface load balancing and failover. IC Role / Device Role / Timing Role: High-availability PCIe switch implementing 1+1 and N+1 failover mechanisms with automatic link retraining and traffic rerouting. Use Value: Dedicated hot-plug controllers and UEC ensure zero-downtime drive replacement and sustained I/O continuity during controller switchover events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable PCIe switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PM41052B-F3EI | 52-lane, 28-port, 26 NTB capacity - higher lane count and NTB density than PM41036B-F3EI. | Targeted at larger enclosures (e.g., 48+ drive systems) requiring greater interconnect bandwidth and NTB concurrency. | Select when scaling beyond 20 ports or needing >18 NTBs; footprint and power envelope differ. |
| PM41028B-F3EI | 28-lane, 16-port, 14 NTB capacity - lower lane count and reduced partitioning (8 virtual partitions). | Suitable for entry-level enclosures (e.g., 8–16 drive systems) with constrained board area and thermal budget. | Choose for cost-optimized, space-constrained designs where 36 lanes and 10 partitions exceed requirements. |
Compared with PM41052B-F3EI and PM41028B-F3EI, the PM41036B-F3EI delivers balanced lane density (36), port count (20), and virtual partitioning (10), making it optimal for mid-tier NVMe enclosures requiring robust error containment and scalable NTB deployment without over-provisioning.
Availability
PM41036B-F3EI is available at Aetrix Electronics and suitable for PCIe SSD enclosures, multi-host NVMe fabrics, high-density blade server I/O aggregation, and enterprise storage controller front-ends requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for PM41036B-F3EI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company delivering smart, connected, and secure embedded control solutions, with leadership in FPGA, analog, interface, and flash memory technologies.
The Switchtec PSX Gen4 family-including PM41036B-F3EI-is designed specifically for high-reliability, software-defined PCIe infrastructure in data center storage, composable systems, and NVMe-MI–enabled enclosures.
FAQ
What is the PCIe generation and data rate supported by the PM41036B-F3EI?
The PM41036B-F3EI supports PCIe Gen4 with a data rate of 16 GT/s per lane. It complies fully with the PCI Express Base Specification Revision 4.0, including link training, equalization, and L0s/L1 power states. All 36 lanes operate at Gen4 speed, and port bifurcation (x1/x2/x4/x8/x16) is supported without generation downshift.
Does the PM41036B-F3EI include an integrated processor, and what is its role?
Yes, the PM41036B-F3EI integrates a MIPS-based embedded processor used exclusively for running enclosure management firmware. This processor executes the NVMe-MI stack, handles SGPIO/LED control, processes SMBus sensor data, and manages hot-plug state machines-eliminating the need for an external microcontroller in compliant NVMe enclosures.
How many Non-Transparent Bridges (NTBs) does the PM41036B-F3EI support, and how are they assigned?
The PM41036B-F3EI supports up to 18 assignable Non-Transparent Bridges. NTBs can be dynamically allocated to any of its 20 ports via configuration registers, enabling flexible peer-to-peer memory-mapped I/O between hosts or between host and accelerator devices without hardware redesign.
What error containment features are implemented in the PM41036B-F3EI?
The PM41036B-F3EI implements Downstream Port Containment (DPC), Completion Timeout Synthesis (CTS), Advanced Error Reporting (AER), and programmable Upstream Error Containment (UEC) on all ports. These features isolate faults at the port level and prevent error propagation to upstream root complexes, ensuring system-level resilience in mission-critical storage deployments.
Is the PM41036B-F3EI compatible with NVMe-MI management standards?
Yes, the PM41036B-F3EI fully supports NVMe-MI via both in-band (using native NVMe enclosure services and SES commands over the PCIe link) and out-of-band (MCTP over I²C) channels. This dual-path capability enables comprehensive health monitoring, firmware updates, and LED/status control without requiring additional management silicon.
What package type and pin count does the PM41036B-F3EI use?
The PM41036B-F3EI uses a 27 mm × 27 mm, 780-ball Fine-Pitch Chip Array Ball Grid Array (FCBGA) package with 1.0 mm ball pitch. The package code "F3EI" denotes this specific mechanical and thermal variant, validated for conduction-cooled and forced-air environments in enterprise storage applications.
PM41036B-F3EI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- Switchtec
- Package/Case:
- 753-BBGA
- Packaging:
- Tray
- Product Status:
- Obsolete
- Applications:
- Controller
- Interface:
- JTAG, MII, RMII, UART, 2-Wire SMBus
- Voltage - Supply:
- -
- Supplier Device Package:
- 753-BBGA (29x29)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
PM41036B-F3EI FAQ
1.How can I place an order for PM41036B-F3EI through Aetrix?
Please submit a Request for Quotation (RFQ) for PM41036B-F3EI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PM41036B-F3EI reliable?
The price and inventory of PM41036B-F3EI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PM41036B-F3EI is usually 5 days.
3.What payment methods are accepted for PM41036B-F3EI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PM41036B-F3EI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PM41036B-F3EI?
PM41036B-F3EI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PM41036B-F3EI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PM41036B-F3EI?
For technical support, including PM41036B-F3EI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PM41036B-F3EI requirements.
6.How does Aetrix verify that PM41036B-F3EI is sourced from the original manufacturer or authorized distributors?
All PM41036B-F3EI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PM41036B-F3EI meets industry standards.
7.What is the process for return or replacement of PM41036B-F3EI?
All PM41036B-F3EI units undergo pre-shipment inspection (PSI). If there is an issue with PM41036B-F3EI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PM41036B-F3EI part is unused and in its original packaging.
Return procedure for PM41036B-F3EI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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