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Microchip Technology PM50028B1-FEI
- Part No.:
- PM50028B1-FEI
- Manufacturer:
- Microchip Technology
- Category:
- Specialized
- Package:
- -
- Datasheet:
-
PM50028B1-FEI.pdf
- Description:
- PFX 28XG5 FANOUT PCIE SWITCH
- Quantity:
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Product details
Overview
PM50028B1-FEI from Microchip Technology is a Gen 5 PCIe fanout switch IC with 28 lanes, 8 virtual switch partitions, and 16 hot-plug controllers-designed for high-reliability interconnect in NVMe storage expansion, edge server I/O aggregation, and telecom baseband units.
For engineers reviewing the PM50028B1-FEI datasheet, PM50028B1-FEI pinout, PM50028B1-FEI application, or PM50028B1-FEI equivalent, key selection criteria include PCIe Gen 5 32 GT/s lane count, NTB support per port, DPC-enabled error containment, and integrated MIPS processor for firmware-managed topology control.
Technical Context
The PM50028B1-FEI implements a non-blocking PCIe Gen 5 switch fabric with cut-through DMA engine supporting up to 64 channels and real-time eye capture for SERDES validation. It integrates an embedded MIPS processor for autonomous management of hot-plug events, NTB address translation, and diagnostics via JTAG/EJTAG or in-band PCIe.
Each of its 16 hot-plug controllers supports SHPC-compliant slot/edge connectors and GPIOs configurable for SFF-8644, OCuLink, or SFF-8639 cable standards. Downstream Port Containment (DPC) and Completion Timeout Synthesis (CTS) are implemented per downstream port to isolate faults without upstream host reset.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| PCIe Generation | Gen 5 compliant at 32 GT/s per lane-enables full x16 host uplink with 2×x8 or 4×x4 downstream splits without bandwidth bottleneck. |
| Total Lanes | 28 bidirectional PCIe lanes-supports configurations such as x16 + 2×x4 + 2×x2 or flexible fanout to 16 endpoints. |
| Virtual Partitions | 8 independent virtual switch partitions-allows hardware-isolated traffic domains for multi-tenant servers or secure I/O virtualization. |
| Hot-Plug Controllers | 16 dedicated controllers-one per downstream port-enables concurrent surprise removal/insertion of NVMe SSDs or mezzanine cards without system reboot. |
| Nontransparent Bridges | Up to 48 assignable NTBs-permits peer-to-peer memory-mapped interconnect across separate PCIe hierarchies (e.g., host-to-FPGA or FPGA-to-FPGA). |
| Integrated Processor | MIPS-based embedded core-executes boot image authentication, runtime diagnostics, and SERDES calibration without external host intervention. |
| Error Containment | Per-port DPC + AER + CTS-prevents single-link failure from propagating to upstream root complex or affecting other active ports. |
Pinout & Package
PM50028B1-FEI is housed in a 27 mm × 27 mm, 780-pin FCBGA package (package code: FCI-780). Pin functions are defined per Microchip's official PM50028B1-FEI Pin List Rev A (DS00003776E, pp. 22–31), including dedicated REFCLK, PERST#, WAKE#, SMBus, UART, TWI, SGPIO, and JTAG/EJTAG signal groups.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| REFCLK_P/N | Differential reference clock input | Accepts 100 MHz differential clock for PCIe PHY synchronization; required for link training compliance. |
| PERST# | Global reset assertion | Active-low asynchronous reset that initializes switch fabric, configuration space, and embedded MIPS core. |
| WAKE# | PCIe wake signal output | Drives low to notify upstream host of hot-plug insertion event; complies with SHPC specification. |
| SMBCLK/SMBDAT | Two-wire interface bus | Provides out-of-band access to configuration registers and temperature/voltage monitoring sensors. |
| TDO/TDI/TMS/TCK | JTAG boundary-scan interface | Enables silicon-level debug, flash programming, and SERDES parameter tuning during bring-up. |
Key Features
| Feature | Design Value |
|---|---|
| Real-time eye capture | On-die oscilloscope capability captures live PCIe Gen 5 waveform integrity at receiver pins-reduces lab validation time by eliminating external BERT setup. |
| Downstream Port Containment (DPC) | Hardware-enforced isolation of faulty downstream links prevents error propagation to upstream root complex or sibling ports-critical for carrier-grade uptime. |
| Boot image authentication | Secure boot using SHA-256 and RSA-2048 validates firmware signature before MIPS core execution-mitigates supply-chain tampering risks. |
| NTB address translation | Configurable BAR sub-windows enable precise memory-mapped I/O between isolated PCIe domains-required for FPGA co-processing or GPU direct RDMA. |
| GPIO configurability | 32 programmable GPIOs support SFF-8485 SGPIO, custom hot-plug signaling, or connector presence detection-adapts to proprietary backplane designs. |
Applications
| Storage Expansion System | Edge Server I/O Aggregation |
|---|---|
Use Scenario: 1U rackmount server expanding a single x16 host slot into eight x4 NVMe U.2 drives via PCIe switch fabric. IC Role / Device Role / Timing Role: PM50028B1-FEI acts as a lane-splitting, hot-plug-aware PCIe Gen 5 switch managing topology discovery, power sequencing, and link equalization. Use Value: Enables concurrent hot-swap of NVMe drives without host reset; DPC ensures one failed drive does not stall remaining seven. | Use Scenario: Telecom edge compute node aggregating x8 FPGA accelerators, x4 10GbE MACs, and x2 SATA controllers onto one CPU PCIe root port. IC Role / Device Role / Timing Role: PM50028B1-FEI serves as a deterministic I/O hub with 8 virtual partitions-assigning dedicated bandwidth and fault domains per function block. Use Value: Hardware partition isolation prevents FPGA firmware crash from disrupting network packet processing or storage I/O paths. |
| Baseband Unit (BBU) | Test & Measurement Rack |
Use Scenario: 5G massive MIMO radio unit requiring low-latency, deterministic PCIe connectivity between DSP array and host controller over extended temperature range. IC Role / Device Role / Timing Role: PM50028B1-FEI provides Gen 5 cut-through switching with ECC-protected on-chip RAM and SERDES margining for -40°C to +105°C operation. Use Value: End-to-end data integrity protection and real-time eye capture allow field validation of signal integrity under thermal stress without external test gear. | Use Scenario: Automated test equipment chassis routing PCIe signals from controller module to 16 instrument modules (oscilloscopes, spectrum analyzers, arbitrary waveform generators). IC Role / Device Role / Timing Role: PM50028B1-FEI operates as a managed fanout switch with 16 hot-plug controllers-enabling dynamic reconfiguration of instrument mix during test sequence changes. Use Value: Surprise-plug capability allows instrument hot-swap mid-test; JTAG/EJTAG access enables in-system firmware update without chassis disassembly. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PCIe fanout switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PM50028B1-FEI-TR | Tape-and-reel packaging variant; identical electrical specs, timing, and firmware compatibility. | No functional difference-used exclusively for automated SMT assembly; same thermal and signal integrity behavior. | Select PM50028B1-FEI-TR only for high-volume production with pick-and-place requirements. |
| PM51028B1-FEI | PSX variant with identical 28-lane, 8-partition, 16-hot-plug spec-but includes enhanced SERDES diagnostics and dual-boot ROM support. | Better suited for systems requiring field-upgradable firmware images or redundant boot paths in safety-critical infrastructure. | Choose PM51028B1-FEI when dual-image boot resilience or advanced SERDES margining is required beyond baseline PFX functionality. |
Compared with PM50028B1-FEI-TR, the base PM50028B1-FEI offers tray packaging for prototyping and low-volume validation; compared with PM51028B1-FEI, it delivers identical switching performance at lower cost where dual-boot or extended diagnostics are unnecessary.
Availability
PM50028B1-FEI is available at Aetrix Electronics and suitable for NVMe storage expansion, edge server I/O aggregation, and 5G baseband units requiring stable component supply, long-term lifecycle commitment, and traceable sourcing.
Supply support for PM50028B1-FEI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog devices, FPGAs, and connectivity solutions-with emphasis on reliability, security, and long-life support for industrial and aerospace markets.
The Switchtec PFX family-including PM50028B1-FEI-is engineered for high-availability PCIe infrastructure in data centers, defense systems, and telecom equipment where fault containment, hot-plug robustness, and firmware authenticity are mandatory.
FAQ
What PCIe generation and data rate does the PM50028B1-FEI support?
The PM50028B1-FEI supports PCIe Gen 5 with a data rate of 32 GT/s per lane. It maintains full backward compatibility with Gen 4 (16 GT/s) and Gen 3 (8 GT/s) devices. Link training automatically negotiates the highest mutually supported speed, and manual PHY configuration is available for signal integrity optimization. This ensures interoperability across mixed-generation systems while delivering maximum bandwidth for NVMe and accelerator interfaces in the PM50028B1-FEI design.
How many virtual switch partitions does the PM50028B1-FEI support, and what is their purpose?
The PM50028B1-FEI supports exactly 8 virtual switch partitions. Each partition operates as an independent PCIe hierarchy with isolated configuration space, memory windows, and error reporting-enabling hardware-enforced resource separation for multi-tenant workloads, secure I/O virtualization, or functional safety domains. This capability is implemented in silicon and requires no host software overhead, making it essential for PM50028B1-FEI deployments in edge servers and telecom infrastructure where isolation guarantees are mandated.
Does the PM50028B1-FEI include built-in error containment features, and which ones are implemented per port?
Yes, the PM50028B1-FEI implements Downstream Port Containment (DPC), Advanced Error Reporting (AER), and Completion Timeout Synthesis (CTS) on every downstream port. DPC isolates faulty links to prevent error propagation; AER logs detailed TLP-level errors; CTS synthesizes completion timeouts to avoid upstream host lockup from stalled non-posted transactions. These features are active by default and require no host driver configuration-making them integral to the PM50028B1-FEI's high-reliability architecture for mission-critical systems.
What type of embedded processor is integrated into the PM50028B1-FEI, and what functions does it perform?
The PM50028B1-FEI integrates a MIPS32-compatible embedded processor core. It executes secure boot validation, runs Switchtec firmware for hot-plug management, performs SERDES calibration, handles real-time eye capture, and manages diagnostics via JTAG/EJTAG or in-band PCIe. The processor operates independently of the host CPU and accesses on-chip SRAM with ECC protection-ensuring deterministic behavior critical for PM50028B1-FEI use in telecom and defense applications where host dependency must be minimized.
Is the PM50028B1-FEI compatible with optical or passive PCIe cables, and which connector standards does it support?
Yes, the PM50028B1-FEI supports passive, managed, and optical PCIe cables through native PHY compliance with SFF-8644, SFF-8643, SFF-8639, and OCuLink specifications. Its GPIOs are configurable for SFF-8485-compliant SGPIO signaling, enabling interoperability with enterprise backplanes and custom cabling. This flexibility is validated in the PM50028B1-FEI datasheet and confirmed across Microchip's Gen 5 evaluation platforms-ensuring reliable link training and equalization across cable types without firmware modification.
PM50028B1-FEI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- Switchtec
- Package/Case:
- -
- Packaging:
- Tray
- Product Status:
- Active
- Applications:
- Fanout PCIe Switch
- Interface:
- 2-Wire, GMII, GPIO, JTAG, PCIe, RMII, UART
- Voltage - Supply:
- -
- Supplier Device Package:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
PM50028B1-FEI FAQ
1.How can I place an order for PM50028B1-FEI through Aetrix?
Please submit a Request for Quotation (RFQ) for PM50028B1-FEI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PM50028B1-FEI reliable?
The price and inventory of PM50028B1-FEI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PM50028B1-FEI is usually 5 days.
3.What payment methods are accepted for PM50028B1-FEI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PM50028B1-FEI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PM50028B1-FEI?
PM50028B1-FEI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PM50028B1-FEI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PM50028B1-FEI?
For technical support, including PM50028B1-FEI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PM50028B1-FEI requirements.
6.How does Aetrix verify that PM50028B1-FEI is sourced from the original manufacturer or authorized distributors?
All PM50028B1-FEI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PM50028B1-FEI meets industry standards.
7.What is the process for return or replacement of PM50028B1-FEI?
All PM50028B1-FEI units undergo pre-shipment inspection (PSI). If there is an issue with PM50028B1-FEI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PM50028B1-FEI part is unused and in its original packaging.
Return procedure for PM50028B1-FEI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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