Microchip Technology PM6104B-FEI

Overview

PM6104B-FEI from Microchip Technology is a 48-channel multi-rate Ethernet MAC/PHY IC supporting 1 GE to 400 GE client rates, 1.2 Tbps aggregate capacity with PAM4 SerDes, integrated MACsec encryption engines, and IEEE 1588v2 Class C/D timestamping for precision timing in 5G and data center interconnect applications.

For engineers reviewing the PM6104B-FEI datasheet, PM6104B-FEI pinout, PM6104B-FEI application, or PM6104B-FEI equivalent, key selection criteria include SerDes count (48), PAM4/NRZ dual-mode support, hitless 2:1 mux capability, FlexE interface readiness, and hardware-accelerated MACsec compliance.

Technical Context

The PM6104B-FEI implements dual-domain SerDes architecture-24 host-side and 24 line-side lanes-with configurable retiming (analog + PCS), forward/reverse gearboxing, and crosspoint switching enabling any-to-any SerDes connectivity. It supports OTN retiming and SyncE alongside Ethernet PHY functions.

It integrates dedicated hardware blocks for IEEE 802.1AE MACsec encryption at line rate, FlexE shim processing for sub-rate client mapping, and PTP timestamping with sub-10 ns accuracy in Class C/D mode-critical for time-sensitive networking in service provider edge and metro aggregation systems.

Key Specifications

Pinout & Package

PM6104B-FEI is housed in a 27 mm × 27 mm, 1156-pin FC-BGA package with controlled impedance routing for high-speed SerDes signaling. Pin assignment follows Microchip's META-DX1 family layout with dedicated power, reference clock, JTAG, and SerDes differential pairs grouped by domain (host/line).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Ethernet MAC/PHY applications.

Compared with PM6104B-FEI, PM6104A-FEI omits FlexE and Interlaken-reducing feature set but lowering cost for basic MAC/PHY roles; PM6108B-FEI adds FlexE scheduling and Interlaken, making it suitable for next-gen DCI where sub-rate client grooming and fabric-side interoperability are mandatory.

Availability

PM6104B-FEI is available at Aetrix Electronics and suitable for high-density router line cards, FlexE-based data center interconnect muxponders, and carrier-grade working/protect switch fabrics requiring stable component supply and long-term lifecycle assurance.

Supply support for PM6104B-FEI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology is a U.S.-based semiconductor company specializing in secure, intelligent, and connected embedded control solutions, with leadership in timing, networking, and security ICs.

The META-DX1 product line delivers high-capacity, multi-protocol Ethernet MAC/PHYs targeting 5G transport, cloud-scale data center interconnect, and carrier edge infrastructure-designed for hardware-accelerated FlexE, MACsec, and precision timing.

FAQ

What Ethernet data rates does the PM6104B-FEI support?

The PM6104B-FEI supports client Ethernet rates from 1 GE to 400 GE across its 48 SerDes lanes. It natively handles 10G, 25G, 40G, 50G, 100G, 200G, and 400G configurations using NRZ or PAM4 signaling. Rate adaptation is managed via integrated gearboxing and crosspoint switching-no external retimers required for mixed-rate line cards.

Does the PM6104B-FEI include hardware-accelerated MACsec encryption?

Yes, the PM6104B-FEI integrates dedicated MACsec engines compliant with IEEE 802.1AE-2018. It performs line-rate encryption and decryption at up to 400G per port with AES-256-GCM ciphers, zero packet loss under full load, and deterministic latency. Key management is handled via secure on-chip registers accessible through the SDK-no external crypto controller needed for PM6104B-FEI deployments.

What is the PTP timestamping accuracy of the PM6104B-FEI?

The PM6104B-FEI achieves IEEE 1588v2 Class C/D compliance with ≤10 ns residual timestamping error in typical operating conditions. This accuracy is enabled by hardware timestamp insertion at the physical layer, low-jitter SerDes clock recovery, and temperature-compensated delay calibration-making PM6104B-FEI suitable for 5G fronthaul synchronization and industrial time-sensitive networking.

Can the PM6104B-FEI operate in hitless 2:1 mux mode?

Yes, the PM6104B-FEI supports hitless 2:1 multiplexing between working and protect signal paths. It synchronizes PTP clocks, aligns packet boundaries, and manages SerDes retraining transparently-ensuring zero packet loss and sub-100 µs switchover. This functionality is implemented entirely in hardware and requires no firmware intervention during failover events involving PM6104B-FEI.

Is FlexE support included in the PM6104B-FEI?

Yes, the PM6104B-FEI includes full hardware FlexE 2.1 support-including calendar scheduling, group/multiplexing/shim processing, and sub-rate client mapping (e.g., 10/25/40/50GE into 400G). FlexE functionality is enabled via configuration registers and SDK APIs; no external FPGA or processor is required to implement FlexE features in PM6104B-FEI-based designs.