My Inquiry
My Account
STMicroelectronics PM6641TR
.jpg)
- Part No.:
- PM6641TR
- Manufacturer:
- STMicroelectronics
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
PM6641TR.pdf
- Description:
- IC REG CONV DDR 3OUT 48VFQFPN
- Quantity:
- Payment:
- Shipping:
Inventory:3,070
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PM6641TR from STMicroelectronics is a monolithic voltage regulator module designed for DDR2/3 memory and chipset power delivery in ultra-mobile PCs. It integrates three independent adjustable buck converters (1.8 V, 1.5 V, 1.05 V), a ±2 A LDO for VTT termination, and a low-noise ±15 mA buffered VTTREF reference. Features include constant-frequency current-mode control, out-of-phase switching, S0–S5 state compliance, and active soft-end discharge.
For engineers reviewing the PM6641TR datasheet, PM6641TR pinout, PM6641TR application, or PM6641TR equivalent, key selection criteria include DDR2/3 termination accuracy (±20 mV at ±1 A), programmable current limit per rail (up to 6.1 A), phase management via SET_PH1, and dual-mode tracking/non-tracking discharge controlled by DSCG.
Technical Context
The PM6641TR implements three independent current-mode synchronous buck regulators with fixed 0.8 V internal reference, programmable switching frequency (500–825 kHz), and minimum on-time as low as 180 ns. Each rail supports external compensation (COMP_x), feedback (VFB_x), soft-start (SS_x), and open-drain Power Good (PG_x) signaling.
Its integrated ±2 A VTT LDO uses VTTFB for closed-loop regulation against VTTREF, while the VTTREF buffer delivers 0.9 V ±2% accuracy referenced to VDDQ/2. The device enforces S3/S5 power-state sequencing via EN_VTT and EN_1S8, and enables discharge path selection (tracking vs. non-tracking) through the DSCG pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 5.5 V - supports direct connection to common system rails (3.3 V, 5 V) without pre-regulation. |
| Output Voltages | 1.8 V (VDDQ), 1.5 V (chipset), 1.05 V (chipset), ±0.9 V (VTT DDR2), ±0.75 V (VTT DDR3) - matches JEDEC DDR2/3 termination requirements. |
| Voltage Reference | 0.8 V ±1% - high-precision internal reference enabling ±1% output regulation across temperature and load. |
| Switching Frequency | 500–825 kHz - selectable via SET_SWF resistor; enables optimization of efficiency vs. EMI and component size. |
| VTT LDO Current Capability | ±2 A peak - sufficient for DDR2/3 parallel termination with foldback current limiting for fault protection. |
| Thermal Protection | 150 °C shutdown with 15 °C hysteresis - prevents permanent damage during sustained overload or poor PCB thermal design. |
| Power Good Accuracy | ±10% window (90–110% of nominal) - ensures reliable system power sequencing and reset assertion. |
Pinout & Package
PM6641TR is housed in a VFQFPN-48 7×7 mm package with exposed thermal pad, optimized for high-density portable PCB layouts and efficient heat dissipation in space-constrained UMPC designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN_1S8, EN_1S5, EN_1S05, EN_VTT | Enable inputs per rail | Control power-up sequencing across S0–S5 states; EN_1S8 active in S0–S3, EN_VTT active only in S0. |
| VFB_1S8 / VFB_1S5 / VFB_1S05 / VTTFB | Feedback inputs | Close regulation loop for each SMPS rail and VTT LDO; support internal/external divider configurations. |
| COMP_1S8 / COMP_1S5 / COMP_1S05 | Compensation outputs | Interface with external RC network to stabilize control loop across load/temperature variations. |
| DSCG | Discharge mode select | Configures VDDQ/VTT soft-end as tracking (DSCG = AVCC) or independent (DSCG = AGND) discharge path. |
| SET_PH1 | Phase control input | Sets relative phase offset between buck regulators to reduce input ripple and improve thermal distribution. |
| CSNS | Current limit setting | Analog input scaling peak current limit threshold for all three SMPS channels via external resistor. |
| PG_1S8 / PG_1S5 / PG_1S05 | Power Good outputs | Open-drain signals indicating valid regulation (90–110% window); used for system power sequencing and fault reporting. |
Key Features
| Feature | Design Value |
|---|---|
| Three independent SMPS rails | 1.8 V (VDDQ), 1.5 V, and 1.05 V outputs with separate enable, feedback, compensation, and Power Good - enables flexible DDR2/3 + chipset supply architecture. |
| DDR2/3-compliant VTT/VTTREF subsystem | ±2 A VTT LDO with VTTFB feedback and ±15 mA buffered VTTREF referenced to VDDQ/2 - meets JEDEC VTT accuracy and noise requirements. |
| Programmable soft-start and soft-end | External capacitor-controlled ramp time per rail; selectable tracking/non-tracking discharge via DSCG - prevents inrush current and bus contention during power transitions. |
| S0–S5 state power management | Dedicated enable pins (EN_1S8, EN_VTT) with defined turn-on/off thresholds - supports ACPI-compliant sleep/wake sequences in UMPC platforms. |
| Pulse-skipping at light load | Automatic transition from PWM to pulse-skipping mode below ~100 mA - maintains >75% efficiency down to microamp quiescent loads. |
Applications
| UMPC DDR2 Memory Supply | UMPC DDR3 Memory Supply |
|---|---|
|
Use Scenario: Powering DDR2 SODIMM modules in sub-10″ ultra-mobile PCs with strict thermal and board area constraints. IC Role / Device Role / Timing Role: Delivers tightly regulated 1.8 V VDDQ and matched ±0.9 V VTT termination synchronized to memory clock domain. Use Value: Achieves ±1% VDDQ regulation and ±20 mV VTT accuracy over –40°C to +85°C, ensuring signal integrity at DDR2 data rates up to 800 MT/s. |
Use Scenario: Supporting DDR3L SO-DIMMs in fanless handheld computing devices requiring low-voltage operation. IC Role / Device Role / Timing Role: Generates 1.5 V VDDQ and ±0.75 V VTT referenced to VDDQ/2, with S3/S5 state-aware enable sequencing. Use Value: Enables compliant DDR3 termination with <15 mV VTTREF drift and <200 ns load transient response, critical for stable 1066 MT/s operation. |
| UMPC Chipset Core Supply | Portable System Power Sequencing |
|
Use Scenario: Providing core voltage to Intel Atom or AMD Geode chipsets in compact UMPC motherboards. IC Role / Device Role / Timing Role: Supplies 1.5 V and 1.05 V rails with independent soft-start, current limiting, and Power Good signaling. Use Value: Guarantees monotonic startup with <1% cross-regulation between rails and <200 ns minimum on-time for stable low-VIN operation. |
Use Scenario: Managing power-state transitions (S0→S3→S5) in battery-powered PDAs and handheld terminals. IC Role / Device Role / Timing Role: Coordinates rail enable/disable timing via EN_1S8, EN_VTT, and DSCG to meet ACPI specification tPLA/tPLD timing windows. Use Value: Reduces S3 exit latency by 30% versus discrete solutions and eliminates external sequencing ICs through integrated logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail DDR memory supply applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6260CRTZ-T | Single 3-output buck controller (no integrated FETs); requires external MOSFETs and gate drivers. | Lacks integrated VTT LDO and VTTREF buffer; needs discrete termination circuitry. | Preferred when higher efficiency (>90% at 5 A) or custom FET selection is required; adds BOM cost and layout complexity. |
| TPS51220ARUKR | Two-buck + VTT LDO solution; no VTTREF buffer; supports only DDR3; max VTT current = ±1.5 A. | Does not support DDR2 VTT (±0.9 V) or S5 state management; limited to 1.35 V VDDQ max. | Valid for DDR3-only designs where 1.5 A VTT suffices and S5 sequencing is unnecessary; smaller footprint but lower feature set. |
Compared with ISL6260CRTZ-T and TPS51220ARUKR, the PM6641TR uniquely integrates full DDR2/3 termination (VTT + VTTREF), triple independent SMPS with phase control, and complete S0–S5 state support in a single VFQFPN-48 package-reducing total solution size by 35% and eliminating six external components.
Availability
PM6641TR is available at Aetrix Electronics and suitable for ultra-mobile PC (UMPC), handheld computing, and portable DDR2/3 memory system designs requiring stable component supply, long-term lifecycle assurance, and qualified automotive-grade traceability.
Supply support for PM6641TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and analog ICs, with over 40 years of innovation in energy-efficient and highly integrated solutions.
The PM6641TR belongs to ST's monolithic VR product line, engineered specifically for space-constrained, thermally sensitive DDR2/3 memory and chipset power delivery in ultra-mobile computing platforms.
FAQ
What is the maximum supported DDR memory type and data rate for PM6641TR?
The PM6641TR supports both DDR2 and DDR3 memory interfaces. For DDR2, it delivers 1.8 V VDDQ and ±0.9 V VTT, enabling operation up to 800 MT/s. For DDR3, it provides 1.5 V VDDQ and ±0.75 V VTT, supporting data rates up to 1066 MT/s. Its VTTREF accuracy (±2%) and low-noise design meet JEDEC AC and DC specifications for both standards.
How does the DSCG pin affect power-down behavior in DDR systems?
The DSCG pin selects between tracking and non-tracking discharge modes during soft-end. When pulled to AVCC, VTT discharges in proportion to VDDQ (tracking), maintaining termination integrity during controlled ramp-down. When tied to AGND, VTT and VDDQ discharge independently (non-tracking), allowing faster, isolated rail shutdown-critical for meeting S3/S5 exit timing in ACPI-compliant UMPCs.
Can PM6641TR operate with input voltage below 3.0 V?
Yes. The PM6641TR supports an input range of 2.7 V to 5.5 V, enabling direct use of single-cell Li-ion (2.7–4.2 V) or regulated 3.3 V system rails. Minimum on-time (180 ns) and current-mode control ensure stable regulation even at 2.7 V VIN, though efficiency drops ~8% compared to 3.3 V operation due to increased conduction losses.
What thermal derating applies above 70°C ambient?
At TA > 70°C, the PM6641TR's maximum continuous output current must be linearly derated from its 25°C rating (6.1 A peak per SMPS rail) based on RthJA = 25 °C/W. With 4 W max power dissipation, junction temperature exceeds 125°C if ambient exceeds 85°C without enhanced PCB copper pour or airflow-designers must implement ≥2 oz inner-layer copper and thermal vias under the exposed pad.
PM6641TR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Converter, DDR
- Voltage - Input:
- 2.7V ~ 5.5V
- Number of Outputs:
- 3
- Voltage - Output:
- 0.8V ~ 5.5V
- Operating Temperature:
- 0°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VFQFPN (7x7)
PM6641TR FAQ
1.How can I place an order for PM6641TR through Aetrix?
Please submit a Request for Quotation (RFQ) for PM6641TR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PM6641TR reliable?
The price and inventory of PM6641TR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PM6641TR is usually 5 days.
3.What payment methods are accepted for PM6641TR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PM6641TR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PM6641TR?
PM6641TR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PM6641TR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PM6641TR?
For technical support, including PM6641TR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PM6641TR requirements.
6.How does Aetrix verify that PM6641TR is sourced from the original manufacturer or authorized distributors?
All PM6641TR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PM6641TR meets industry standards.
7.What is the process for return or replacement of PM6641TR?
All PM6641TR units undergo pre-shipment inspection (PSI). If there is an issue with PM6641TR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PM6641TR part is unused and in its original packaging.
Return procedure for PM6641TR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PM6641TR Tags
-
TPS51206DSQR
Texas Instruments
-
TPS51200DRCR
Texas Instruments
-
TPS51200DRCT
Texas Instruments
-
TPS62740DSSR
Texas Instruments
-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi
-
RT9026GSP
Richtek USA Inc.
-
LP2998MRX/NOPB
Texas Instruments
-
TPS51200QDRCRQ1
Texas Instruments
-
DPA423GN-TL
Power Integrations
-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
