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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear + Switching

STMicroelectronics PM6675ASTR

Name: PM6675ASTR
Brand: STMicroelectronics
SKU: PM6675ASTR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: PM6675ASTR

Manufacturer:: STMicroelectronics

Category:: Voltage Regulators - Linear + Switching

Package:: 24-VFQFN Exposed Pad

Datasheet:: PM6675ASTR.pdf

Description:: IC REG DL BCK/LNR 33KHZ 24VFQFPN

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Product details

Overview

PM6675ASTR from STMicroelectronics is a dual-output power management IC integrating a high-efficiency constant-on-time (COT) step-down controller and an independent 2 A peak sink/source LDO regulator in a single VFQFPN-24 package. It supports 4.5–36 V input, delivers adjustable 0.6–3.3 V or fixed 1.5 V SMPS output, and features ±1 A/±2 A selectable LDO current limits, 1.237 V ±1 % reference, and 33 kHz no-audible pulse-skip mode - used in industrial 24 V systems and embedded computer power rails.

For engineers reviewing the PM6675ASTR datasheet, PM6675ASTR pinout, PM6675ASTR application, or PM6675ASTR equivalent, this device enables fast transient response with ceramic-capacitor-compatible COT control, lossless R_DS(ON) current sensing, independent soft-start/soft-end sequencing, and dual open-drain power-good signals for system-level rail monitoring and sequencing.

Technical Context

The switching section uses a pseudo-fixed-frequency constant-on-time architecture with embedded integrator-based ripple compensation to maintain DC regulation accuracy despite output voltage ripple - enabling stable operation with low-ESR ceramic capacitors. Its no-R_SENSE current sensing relies on low-side MOSFET R_DS(ON), and includes latched OVP/UVP, negative current limit, and selectable pulse-skip or 33 kHz no-audible mode.

The LDO section operates independently with dedicated enable (LEN), remote sense (LFB), power-good (LPG), and current-limit selection (LILIM). It supports ±1 A or ±2 A peak sink/source capability, soft-end discharge via internal 15–35 Ω resistance, and maintains stability with ≥20 µF ceramic output capacitance - all while sharing only ground and thermal pad with the SMPS section.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Range	4.5 V to 36 V - supports wide industrial 24 V bus with margin for transients and ripple.
SMPS Output Options	Fixed 1.5 V or adjustable 0.6 V–3.3 V - eliminates external feedback divider for default 1.5 V rail generation.
LDO Output Current	±1 A or ±2 A peak - selectable via LILIM pin; enables bidirectional current handling for DDR termination or bias rails.
Reference Voltage	1.237 V ±1 % - high-accuracy bandgap reference used for both SMPS and LDO feedback paths.
Switching Frequency	Min 33 kHz (no-audible mode) - avoids audible noise in sensitive audio or display applications.
Soft-Start Time	Internally fixed at 3 ms - ensures controlled ramp-up without external timing components.
Power-Good Accuracy	±10 % window for both SMPS (SPG) and LDO (LPG) - provides reliable system sequencing and fault detection.

Pinout & Package

VFQFPN-24 4×4 mm package with exposed thermal pad; RoHS-compliant, moisture-sensitive level 3.

Pin/Terminal	Circuit Role	Design Meaning
1 LGND	LDO power ground	Separate ground return for LDO section; must connect to VTT capacitor negative terminal.
2 LFB	LDO remote sense	Enables accurate load regulation by sensing voltage directly at point-of-load via low-noise trace.
3 NOSKIP	Mode selector	Configures PWM / pulse-skip / 33 kHz no-audible mode; logic thresholds defined per datasheet Table 6.
4 LPG	LDO power-good output	Open-drain signal active high when LDO output is within ±10 % of nominal - used for system enable sequencing.
5 SGND	Analog/thermal ground reference	Common analog ground for VREF, COMP, and control logic; must tie to thermal pad and low-impedance plane.
6 AVCC	+5 V internal logic supply	Requires RC filter from +5 V rail; powers analog blocks and digital control logic.
7 VREF	1.237 V reference output	Stable, low-noise reference for feedback networks; max 50 µA load; bypass with 100 nF to SGND.
8 VOSC	Frequency setting input	Resistor-divider tap sets switching frequency; floating not allowed; defines COT timing baseline.
9 VSNS	SMPS remote sense/discharge	Connects near load for accurate regulation; also serves as discharge path during soft-end.
10 VSEL	Output mode selector	Voltage >4 V selects fixed 1.5 V; <4 V enables adjustable mode using external resistor divider.
11 COMP	SMPS error amplifier compensation	External RC network sets loop stability; required for adjustable output configurations.
12 LILIM	LDO current limit select	Tie to SGND for ±1 A, to +5 V for ±2 A peak sink/source capability.
13 SWEN	SMPS enable	Active-high; grounding performs controlled soft-end discharge of SMPS output.
14 LEN	LDO enable	Active-high; grounding initiates independent soft-end discharge of LDO output.
15 SPG	SMPS power-good output	Open-drain signal active high when SMPS output is within ±10 % - used for processor reset or downstream enable.
16 PGND	SMPS power ground	High-current return path for switching section; separate from LGND and SGND.
17 LGATE	Low-side gate driver output	Drives synchronous rectifier MOSFET; 0.6–0.9 Ω pulldown resistance ensures fast turn-off.
18 VCC	+5 V low-side gate driver supply	Bypass with 100 nF to PGND; powers LGATE driver stage.
19 CSNS	Current sense input	Connects to low-side MOSFET source via sense resistor; enables lossless R_DS(ON) current monitoring.
20 PHASE	Switch node	Connection point between high- and low-side MOSFETs; also supplies bootstrap charge path.
21 HGATE	High-side gate driver output	Drives upper MOSFET; 1.8–2.7 Ω pulldown ensures shoot-through prevention.
22 BOOT	Bootstrap capacitor connection	Provides floating supply for HGATE driver; requires 100 nF ceramic capacitor to PHASE.
23 LIN	LDO input	Accepts SMPS output or auxiliary rail; bypass with 10 µF ceramic capacitor to LGND for noise rejection.
24 LOUT	LDO output	Delivers regulated output; requires ≥20 µF (2×10 µF MLCC) ceramic capacitor for stability.

Key Features

Feature	Design Value
Constant-on-time (COT) control	Enables sub-µs load transient response without external compensation components - critical for CPU/GPU core rails.
R_DS(ON)-based current sensing	Eliminates sense resistor and associated power loss - improves efficiency and reduces BOM count in high-current designs.
Dual independent soft-start/soft-end	Prevents inrush current and uncontrolled rail collapse during enable/disable - essential for multi-rail sequencing in embedded systems.
No-audible 33 kHz pulse-skip mode	Suppresses mechanical vibration in ceramic capacitors and magnetics - required for noise-sensitive graphic card and display power supplies.
Independent SMPS and LDO power-good signals	Enables precise, asynchronous rail monitoring and fault isolation - simplifies system-level power management firmware.

Applications

Industrial 24 V Power Distribution

Graphics Card Core & Memory Rails

Use Scenario: Powering PLC I/O modules, motor drivers, and fieldbus interfaces from unregulated 24 V industrial bus with high transient immunity.

IC Role / Device Role / Timing Role: Dual-output PMIC providing isolated 1.5 V logic rail (SMPS) and 1.2 V DDR termination (LDO), with independent sequencing and fault reporting.

Use Value: Eliminates need for two discrete regulators and external sequencing ICs - reduces board area by 35 % and improves startup reliability under brownout conditions.

Use Scenario: Delivering tightly regulated, low-noise power to GPU core and GDDR memory on PCIe graphics cards.

IC Role / Device Role / Timing Role: SMPS supplies high-current GPU core voltage with fast transient response; LDO supplies clean, low-ripple DDR VTT with bidirectional current capability.

Use Value: 33 kHz no-audible mode prevents coil whine during gaming; ±2 A LDO current limit supports dynamic DDR termination without external FETs.

Embedded Computer Systems

Automotive Infotainment Head Units

Use Scenario: Powering ARM-based SBCs (e.g., i.MX6/8) requiring multiple synchronized rails including core, I/O, and DDR.

IC Role / Device Role / Timing Role: Integrated SMPS+LDO replaces discrete buck + LDO + sequencer; SPG/LPG signals feed FPGA or PMIC supervisor for coordinated power-up.

Use Value: Reduces component count by 7 parts vs. discrete solution; 3 ms soft-start meets JEDEC JESD78 latch-up immunity requirements.

Use Scenario: Supplying infotainment SoC, display interface, and audio codec in automotive head units operating across -40°C to +85°C ambient.

IC Role / Device Role / Timing Role: SMPS generates 1.1 V SoC core rail; LDO delivers 1.8 V I/O rail with ±1 A current limit and remote sensing for display panel bias.

Use Value: Junction temperature rating up to 125°C and -40°C startup guarantee operation in sealed dash environments; thermal shutdown at 150°C prevents damage during thermal overload.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output power management applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS51200DRCR	Single-channel DDR termination regulator only; no integrated SMPS controller - requires external buck IC.	Limited to DDR VTT/VREF; cannot replace full PM6675ASTR functionality in multi-rail systems.	Select only when LDO-only function suffices and SMPS is already implemented elsewhere.
ISL6269CRZ	Integrated dual-phase buck controller + LDO; higher pin count (40-QFN); no no-audible mode or R_DS(ON) sensing.	Targeted at laptop CPU VRMs; lacks industrial-grade voltage range (max 24 V input) and extended temp support.	Consider only for consumer portable designs where 33 kHz noise suppression is unnecessary.

Compared with TPS51200DRCR and ISL6269CRZ, PM6675ASTR uniquely integrates a wide-input COT buck controller and bidirectional LDO in one 24-pin VFQFPN, offering superior transient response, industrial voltage range, and no-audible operation - making it optimal for space-constrained embedded and industrial power systems.

Availability

PM6675ASTR is available at Aetrix Electronics and suitable for industrial 24 V power distribution, graphics card core/memory rails, and embedded computer systems requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for PM6675ASTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, microcontrollers, and analog ICs for industrial, automotive, and consumer markets.

The PM6675AS belongs to ST's high-density power management IC portfolio, designed specifically for space-constrained embedded systems requiring dual-rail integration, fast transient response, and robust industrial operating conditions.

FAQ

What is the maximum allowable input voltage for PM6675ASTR?

The absolute maximum input voltage (VIN) is 38 V, but the recommended operating range is 4.5 V to 36 V per datasheet Table 5. Operation above 36 V risks exceeding thermal limits and violating UVLO hysteresis margins - sustained use beyond 36 V is not advised even if within absolute maximum ratings.

Can the LDO output be used independently of the SMPS section?

Yes. The LDO input (LIN) accepts either the SMPS output or an independent lower-voltage rail (e.g., 3.3 V or 5 V), allowing standalone operation. When SWEN is grounded, the SMPS shuts down with soft-end, while LEN-controlled LDO remains fully functional - confirmed in Section 7.2 and Figure 16 of the datasheet.

How is the switching frequency set, and what is its tolerance?

Frequency is set by a resistor divider connected to VOSC (Pin 8); typical range is 300–600 kHz depending on divider ratio and load. Datasheet Figure 6 shows ±15 % variation over load and temperature; no factory trimming is performed - design must accommodate this tolerance in EMI filtering and inductor selection.

Does PM6675ASTR support ceramic output capacitors for both SMPS and LDO sections?

Yes. The SMPS section explicitly supports all-ceramic designs (Section 8.1.7), and the LDO requires ≥20 µF ceramic capacitance (2×10 µF MLCC) on LOUT (Pin 24) for stability per Table 2 and Section 7.2. Electrolytic capacitors are not required or recommended for either output.

PM6675ASTR Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Topology:: Step-Down (Buck) (1), Linear (LDO) (1)

Number of Outputs:: 2

Frequency - Switching:: Down to 33kHz

Voltage/Current - Output 1:: Controller

Voltage/Current - Output 2:: 0.6V ~ 3.3V, 2A

Voltage/Current - Output 3:: -

w/LED Driver:: No

w/Supervisor:: No

w/Sequencer:: No

Voltage - Supply:: 4.5V ~ 36V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-VFQFPN (4x4)

PM6675ASTR FAQ

1.How can I place an order for PM6675ASTR through Aetrix?

Please submit a Request for Quotation (RFQ) for PM6675ASTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PM6675ASTR reliable?

The price and inventory of PM6675ASTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PM6675ASTR is usually 5 days.

3.What payment methods are accepted for PM6675ASTR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PM6675ASTR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PM6675ASTR?

PM6675ASTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PM6675ASTR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PM6675ASTR?

For technical support, including PM6675ASTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PM6675ASTR requirements.

6.How does Aetrix verify that PM6675ASTR is sourced from the original manufacturer or authorized distributors?

All PM6675ASTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PM6675ASTR meets industry standards.

7.What is the process for return or replacement of PM6675ASTR?

All PM6675ASTR units undergo pre-shipment inspection (PSI). If there is an issue with PM6675ASTR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PM6675ASTR part is unused and in its original packaging.

Return procedure for PM6675ASTR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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