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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear + Switching

STMicroelectronics PM6675STR

Name: PM6675STR
Brand: STMicroelectronics
SKU: PM6675STR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: PM6675STR

Manufacturer:: STMicroelectronics

Category:: Voltage Regulators - Linear + Switching

Package:: 24-VFQFN Exposed Pad

Datasheet:: PM6675STR.pdf

Description:: IC REG DL BCK/LNR 33KHZ 24VFQFPN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

PM6675STR from STMicroelectronics is a dual-output power management IC integrating a high-efficiency constant-on-time (COT) step-down controller and an independent 2 A peak-sink/source LDO regulator in a single VFQFPN-24 package. It supports 4.5–28 V input, delivers adjustable 0.6–3.3 V SMPS output (or fixed 1.5 V), and provides ±1 A or ±2 A programmable LDO current limit with dedicated power-good signals for both sections.

For engineers reviewing the PM6675STR datasheet, PM6675STR pinout, PM6675STR application, or PM6675STR equivalent, this device is selected for notebook CPU core voltage regulation, GPU auxiliary rail generation, embedded system multi-rail sequencing, and audio-sensitive applications requiring 33 kHz no-audible pulse-skip mode.

Technical Context

The SMPS section uses a COT architecture with R_DS(ON)-based current sensing, enabling fast transient response without external sense resistors. Output ripple compensation via integrator-based error correction ensures stability with ceramic capacitors and maintains DC accuracy despite AC ripple.

The LDO section features independent soft-start/soft-end, remote sensing (LFB), and selectable ±1 A/±2 A current limits via LILIM pin. Both regulators provide open-drain PGOOD outputs (SPG/LPG) with ±10% window detection and latched OVP/UVP protection.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Range	4.5 V to 28 V - supports wide-input industrial and computing rails including 5 V, 12 V, and 19 V adapter inputs.
SMPS Output Voltage	Fixed 1.5 V or adjustable 0.6 V–3.3 V - enables direct CPU/GPU core voltage setting or flexible point-of-load adjustment.
LDO Output Current Limit	Selectable ±1 A or ±2 A peak - allows matching load transients in memory I/O or analog subsystems without overdesign.
Reference Voltage Accuracy	1.237 V ±1% - ensures tight output regulation across temperature and line variations for precision rails.
Switching Frequency	Configurable up to 600 kHz; 33 kHz minimum in No-Audible mode - eliminates audible noise in thin-client and portable designs.
Soft-Start Time	Internally fixed at 3 ms - prevents inrush current during power-up in multi-rail systems with strict sequencing requirements.
Thermal Shutdown	150 °C junction temperature - protects against sustained overload or poor PCB thermal design without external circuitry.

Pinout & Package

VFQFPN-24 4×4 mm package with exposed thermal pad (PGND/LGND connected to pad); RoHS-compliant, moisture sensitivity level 3.

Pin	Circuit Role	Design Meaning
1 LGND	LDO power ground	Low-impedance return path for LDO output current; must connect to thermal pad and local VTT capacitor ground.
2 LFB	LDO remote sense	Enables accurate load regulation by sensing voltage directly at the load; requires short, low-noise PCB trace.
3 NOSKIP	Mode selector	Configures PWM / Pulse-Skip / No-Audible (33 kHz) operation - critical for EMI and acoustic noise control.
4 LPG	LDO power-good output	Open-drain signal asserted high when LDO output is within ±10% of target - used for system enable sequencing.
5 SGND	Analog reference ground	Common reference for VREF, COMP, VSNS, and internal bandgap; must tie to thermal pad and low-impedance plane.
6 AVCC	+5 V logic supply	Powers internal logic and control circuits; requires RC filter to suppress switching noise coupling.
7 VREF	1.237 V reference output	High-accuracy reference for feedback networks and multilevel pin thresholds; 100 nF bypass to SGND required.
8 VOSC	Frequency selection	Resistor-divider input sets switching frequency; floating connection prohibited - ensures stable oscillator operation.
9 VSNS	SMPS remote sense	Compensates for IR drop between regulator and load; connects directly to load for <±1% regulation accuracy.
10 VSEL	Output mode select	Voltage >4 V selects fixed 1.5 V; <4 V enables adjustable mode using external resistor divider on VSEL/COMP.
11 COMP	SMPS error amplifier output	Compensation node for loop stability; external RC network sets bandwidth and phase margin for ceramic output caps.
12 LILIM	LDO current limit select	Tied to SGND for ±1 A, to +5 V for ±2 A - configures peak sink/source capability without external components.
13 SWEN	SMPS enable	Active-high digital enable; pull low to disable SMPS with controlled soft-end discharge (25 Ω internal path).
14 LEN	LDO enable	Active-high digital enable; pull low to disable LDO with independent soft-end discharge (25 Ω internal path).
15 SPG	SMPS power-good output	Open-drain signal asserted high when SMPS output is within ±10% - used for processor reset or downstream enable.
16 PGND	SMPS power ground	High-current return for HGATE/LGATE drivers and PHASE node; separate from LGND to avoid noise coupling.
17 LGATE	Low-side gate driver	Drives synchronous rectifier MOSFET; 0.6–0.9 Ω pull-down resistance enables fast turn-off and shoot-through prevention.
18 VCC	LGATE supply	+5 V supply for low-side driver; bypassed with 100 nF capacitor to PGND for clean gate drive waveform.
19 CSNS	Current sense input	Connects to MOSFET drain to sense R_DS(ON) voltage drop; sets current limit threshold without external shunt.
20 PHASE	Switch node	Connection point between high/low-side MOSFETs; carries high di/dt; requires minimized loop area for EMI reduction.
21 HGATE	High-side gate driver	Drives upper MOSFET; 1.8–2.7 Ω pull-down resistance ensures robust dead-time control and anti-cross-conduction.
22 BOOT	Bootstrap supply	Provides floating supply for HGATE; requires 100 nF ceramic capacitor between BOOT and PHASE for reliable high-side drive.
23 LIN	LDO input	Accepts 1.5–5.5 V input; bypassed with 10 µF ceramic capacitor to LGND for low-noise LDO operation.
24 LOUT	LDO output	Delivers regulated output; requires 20 µF (2×10 µF MLCC) output capacitance for stability and transient response.

Key Features

Feature	Design Value
Constant-On-Time (COT) control	Enables sub-1 µs load transient response without external compensation - critical for CPU/GPU dynamic voltage scaling.
R_DS(ON) current sensing	Eliminates sense resistor losses and board space; supports efficient high-current designs up to 8 A SMPS output.
No-Audible Pulse-Skip mode	Fixes minimum switching frequency at 33 kHz - prevents coil whine in ultrabooks and silent desktop systems.
Independent soft-start/soft-end	3 ms SMPS soft-start and active discharge paths (25 Ω) for both regulators - ensures glitch-free power sequencing.
Dual PGOOD signals	Separate SPG and LPG open-drain outputs with ±10% windows - enables independent monitoring and fault isolation.
Ceramic capacitor support	Stable operation with low-ESR MLCCs on both SMPS and LDO outputs - reduces solution size and improves reliability.

Applications

Application 1

Application 2

Use Scenario: Core voltage regulation for Intel Core i5/i7 mobile processors in ultrabooks.

IC Role / Device Role / Timing Role: Primary SMPS controller delivering dynamically scaled 0.6–1.5 V CPU V_DD with fast transient response.

Use Value: COT architecture achieves <100 ns load-step recovery, meeting Intel IMVP-6+ VRD spec for 10 A/µs slew rates.

Use Scenario: GPU memory I/O voltage (VDDQ) supply on discrete graphics cards.

IC Role / Device Role / Timing Role: Dual-rail source: SMPS for 1.25 V VDDQ, LDO for clean 0.9 V termination bias.

Use Value: Independent LDO soft-end prevents data corruption during GPU power-down sequences.

Application 3

Application 4

Use Scenario: Multi-rail power for ARM-based embedded computers (e.g., NVIDIA Jetson).

IC Role / Device Role / Timing Role: Single-package solution generating 1.8 V SoC core, 1.2 V DDR, and 0.9 V analog rails.

Use Value: Shared AVCC/SGND infrastructure and synchronized soft-start reduce BOM count and layout complexity.

Use Scenario: Audio subsystem bias supply in noise-sensitive medical imaging terminals.

IC Role / Device Role / Timing Role: LDO section provides ultra-low-noise 3.3 V AVDD for ADC/DAC reference buffers.

Use Value: No-Audible mode eliminates 20–20 kHz switching artifacts that would modulate sensitive analog front-ends.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output power management applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS51220ARUKT	Single-channel COT controller only; no integrated LDO - requires external linear regulator for second rail.	Lacks independent LDO PGOOD and soft-end; unsuitable for strict sequencing-critical applications.	Choose when cost sensitivity outweighs integration benefits and LDO functionality is handled externally.
ISL95831IRZ	Includes integrated MOSFETs (buck converter), but no LDO - higher integration at expense of flexibility and thermal separation.	Cannot support independent LDO current limiting or remote sensing; limited to fixed 1.5 V/1.05 V outputs.	Prefer for compact, low-component-count designs where LDO functionality is unnecessary or implemented separately.

Compared with TPS51220ARUKT and ISL95831IRZ, PM6675STR uniquely combines a controller-grade SMPS with a fully featured 2 A LDO in one package, enabling true dual-rail independence, precise sequencing, and noise-isolated bias generation without external components.

Availability

PM6675STR is available at Aetrix Electronics and suitable for notebook computers, graphic cards, and embedded computers requiring stable component supply, long-term lifecycle support, and automotive-qualified thermal performance (−40°C to +125°C junction).

Supply support for PM6675STR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, microcontroller, power, and sensor solutions for industrial, automotive, and consumer markets.

The PM6675STR belongs to ST's Power Management – DC-DC Controllers product line, engineered specifically for high-density, multi-rail computing and graphics power delivery with emphasis on transient response, acoustic noise suppression, and system-level sequencing integrity.

FAQ

What is the maximum supported SMPS output current for PM6675STR?

The PM6675STR is a controller IC-not a converter with integrated MOSFETs-so its SMPS output current is determined by external high/low-side MOSFET selection, inductor rating, and thermal design. With appropriate 30 V MOSFETs and 1 µH inductor, it reliably supports up to 8 A continuous output, as validated in typical application circuits and load transient waveforms (Fig. 25–28).

Can the LDO and SMPS sections operate independently?

Yes. The LDO (enabled via LEN pin) and SMPS (enabled via SWEN pin) have fully independent control, soft-start, soft-end, power-good signaling (LPG/SPG), and current limiting. They share only AVCC, SGND, and thermal substrate-enabling staggered startup, fault isolation, and mixed-mode operation (e.g., SMPS active while LDO disabled).

How is output voltage accuracy maintained with ceramic capacitors?

The PM6675STR embeds an integrator-based ripple compensation loop that actively cancels DC error induced by ceramic capacitor ESR zero. This is implemented in the COMP amplifier path and confirmed in Section 7.1.2 of the datasheet, ensuring ±1% regulation accuracy even with zero-ESR MLCCs across full load and line ranges.

Does PM6675STR support I²C or PMBus configuration?

No. PM6675STR is a hardware-configured analog controller: output voltages, current limits, and operating modes are set via resistor dividers (VSEL, VOSC), pin strapping (NOSKIP, LILIM), and external compensation (COMP). It lacks digital interfaces, serial configuration, or programmable registers.

PM6675STR Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Topology:: Step-Down (Buck) (1), Linear (LDO) (1)

Number of Outputs:: 2

Frequency - Switching:: Down to 33kHz

Voltage/Current - Output 1:: Controller

Voltage/Current - Output 2:: 0.6V ~ 3.3V, 2A

Voltage/Current - Output 3:: -

w/LED Driver:: No

w/Supervisor:: No

w/Sequencer:: No

Voltage - Supply:: 4.5V ~ 28V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-VFQFPN (4x4)

PM6675STR FAQ

1.How can I place an order for PM6675STR through Aetrix?

Please submit a Request for Quotation (RFQ) for PM6675STR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PM6675STR reliable?

The price and inventory of PM6675STR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PM6675STR is usually 5 days.

3.What payment methods are accepted for PM6675STR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PM6675STR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PM6675STR?

PM6675STR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PM6675STR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PM6675STR?

For technical support, including PM6675STR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PM6675STR requirements.

6.How does Aetrix verify that PM6675STR is sourced from the original manufacturer or authorized distributors?

All PM6675STR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PM6675STR meets industry standards.

7.What is the process for return or replacement of PM6675STR?

All PM6675STR units undergo pre-shipment inspection (PSI). If there is an issue with PM6675STR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PM6675STR part is unused and in its original packaging.

Return procedure for PM6675STR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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