STMicroelectronics PM6680ATR

Overview

PM6680ATR from STMicroelectronics is a dual synchronous step-down controller with integrated 5 V/100 mA LDO, designed for FPGA and embedded system power rails. It delivers two independently adjustable outputs (OUT1: 0.9–5.5 V; OUT2: 0.9–3.3 V), operates from 6–36 V input, features valley current sensing via R_DS(on), and includes latched OVP/UVP, thermal shutdown, and soft-start (2 ms fixed).

For engineers reviewing the PM6680ATR datasheet, PM6680ATR pinout, PM6680ATR application, or PM6680ATR equivalent, key selection criteria include its constant-on-time architecture for fast transient response, selectable pulse-skip mode (including ultrasonic 33 kHz minimum), independent PGOOD signals, and VFQFPN-32 5×5 mm exposed-pad package for thermal performance in high-density DC/DC modules.

Technical Context

The PM6680ATR implements a constant-on-time (COT) PWM control architecture with voltage feed-forward, enabling near-constant switching frequency across input/output variations and sub-1 µs load transient response. Each buck section uses valley current sensing via low-side MOSFET R_DS(on), eliminating external sense resistors while maintaining accuracy down to light loads.

It integrates an internal 1.237 V ±1% reference (VREF), a 5 V LDO (LDO5) capable of 100 mA peak output, and configurable protections including latched overvoltage (112–120% of VREF), undervoltage (65–71% of VREF), and thermal shutdown at 150 °C. The SKIP pin selects between PWM, pulse-skip, and no-audible skip modes with minimum 33 kHz frequency enforcement.

Key Specifications

Pinout & Package

PM6680ATR is housed in a VFQFPN-32 5×5 mm package with exposed thermal pad, optimized for high-power density and thermal dissipation in compact DC/DC modules.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buck controller applications.

Compared with TPS546B24A and ISL6269, PM6680ATR uniquely combines dual adjustable buck control, integrated 5 V/100 mA LDO, valley-current sensing, ultrasonic pulse-skip, and latched protections in a thermally enhanced 5×5 mm package - making it optimal for space-constrained, reliability-critical industrial and FPGA power systems.

Availability

PM6680ATR is available at Aetrix Electronics and suitable for FPGA system power, industrial 24 V embedded systems, and high-density DC/DC modules requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for PM6680ATR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and analog ICs for industrial, automotive, and embedded markets.

The PM6680ATR belongs to ST's high-efficiency DC/DC controller product line, engineered specifically for FPGA, PLC, and industrial automation power systems demanding dual-rail flexibility, robust protection, and thermal efficiency in compact form factors.

FAQ

What is the purpose of the V5SW pin, and how does it affect LDO5 operation?

V5SW controls LDO5 bypass behavior: when tied to an external 5 V source >4.9 V, the internal 3 Ω switch connects LDO5 directly to that source and disables the linear regulator, reducing power loss. When grounded, LDO5 remains active. This enables efficiency optimization in systems where OUT1 or another rail can supply clean 5 V.

How does the PM6680ATR achieve fast load transient response without external compensation?

It uses constant-on-time (COT) control with voltage feed-forward, where on-time is dynamically adjusted based on VIN and VOUT. The output capacitor's ESR ripple serves as the current-sense signal, eliminating the need for external compensation components while achieving sub-microsecond transient recovery - confirmed in Figure 17 (0→2 A step on OUT1).

Can the two buck sections operate at different switching frequencies, and how is this configured?

Yes - the FSEL pin selects three frequency pairs: 200/300 kHz, 300/400 kHz, or 400/500 kHz for OUT1/OUT2 respectively. This allows optimizing EMI and inductor size per rail (e.g., higher frequency for low-current OUT2, lower for high-current OUT1), with no additional configuration pins required.

What protection features are latched versus auto-recovering, and how is fault clearing handled?

OVP and UVP are latched - once triggered, the affected channel shuts down permanently until SHDN or ENx is cycled. Thermal shutdown is auto-recovering: operation resumes after junction temperature falls below hysteresis threshold (~140 °C). Latched faults require explicit reset via enable or shutdown pin toggling to ensure system safety integrity.