Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear + Switching

STMicroelectronics PM6681A

Name: PM6681A
Brand: STMicroelectronics
SKU: PM6681A
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: PM6681A

Manufacturer:: STMicroelectronics

Category:: Voltage Regulators - Linear + Switching

Package:: 32-VFQFN Exposed Pad

Datasheet:: PM6681A.pdf

Description:: IC REG QUAD BUCK/LINEAR 32VFQFPN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,006

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

PM6681A from STMicroelectronics is a dual synchronous step-down controller with integrated 5 V and adjustable (0.9–3.3 V) LDOs, designed for FPGA and embedded system power rails. It delivers two independently regulated outputs (OUT1: 0.9–5 V; OUT2: 0.9–3.3 V), supports lossless R_DS(on) current sensing, features constant on-time architecture for fast transient response, and operates across 6–36 V input range.

For engineers reviewing the PM6681A datasheet, PM6681A pinout, PM6681A application, or PM6681A equivalent, key selection considerations include its dual-channel COT control, selectable pulse-skip/no-audible-skip modes, independent Power Good signals, 1.237 V ±1% reference, and VFQFPN-32 package with exposed thermal pad.

Technical Context

The PM6681A implements a constant on-time (COT) PWM control architecture per channel, using output ripple voltage for timing-enabling near-fixed frequency operation without external compensation. Each channel includes an embedded integrator loop that compensates DC error from output ripple, ensuring stable regulation under varying load and ESR conditions.

It integrates two high-side/low-side gate drivers (HGATE1/LGATE1 and HGATE2/LGATE2), dual independent current limit circuits with negative current detection, soft-start (2 ms fixed), soft-output discharge, latched UVP, and not-latched OVP. The FSEL pin selects among three switching frequencies, while SKIP configures PWM, pulse-skip, or ultrasonic (>33 kHz) operation.

Key Specifications

Parameter	Value and Actual Design Meaning
Input voltage range	6 V to 36 V - supports industrial 24 V bus and wide-battery-input systems without pre-regulation.
OUT1 adjustable range	0.9 V to 5 V - powers core logic, DDR termination, or CPU I/O rails with external resistor divider.
OUT2 adjustable range	0.9 V to 3.3 V - supplies FPGA I/O banks or auxiliary logic with independent feedback (FB2).
LDO5 output	Fixed 5 V / 100 mA peak - powers internal gate drivers and external circuitry; bypassable via V5SW pin.
Adjustable LDO output	0.9 V to 3.3 V / 100 mA peak - configurable low-noise bias rail for analog subsystems or reference buffers.
Reference voltage	1.237 V ±1 % - high-accuracy internal reference used for both FB loops and LDO feedback.
Quiescent power	≤5 mW - enables ultra-low-power standby in battery-backed industrial controllers.

Pinout & Package

Package: VFQFPN-32 (5 mm × 5 mm) with exposed thermal pad - optimized for high-power density and thermal performance in compact DC-DC modules.

Pin/Terminal	Circuit Role	Design Meaning
EN1, EN2	Independent enable inputs	High-logic (>2.4 V) activates each buck channel; low (<0.8 V) disables with forced low-side-on state.
FB1, FB2	Voltage feedback inputs	Resistive dividers set OUT1 (0.9–5 V) and OUT2 (0.9–3.3 V); referenced to 1.237 V internal VREF.
HGATE1/2, LGATE1/2	Gate driver outputs	Drive external N-channel MOSFETs; HGATE is floating, LGATE referenced to PGND; R_DS(on) < 3 Ω.
CSENSE1/2	Positive current sense inputs	Connect to synchronous rectifier drain for R_DS(on)-based lossless current limiting and zero-crossing detection.
PGOOD1, PGOOD2	Open-drain status outputs	Assert low when respective output deviates >±10 % from target - enables sequencing and fault monitoring.
SKIP, FSEL	Mode configuration pins	SKIP selects PWM/pulse-skip/no-audible-skip; FSEL sets one of three switching frequencies per channel.

Key Features

Feature	Design Value
Constant on-time (COT) control	Enables sub-10 µs load transient response without external loop compensation components.
Output ripple compensation	Embedded integrator corrects DC offset caused by capacitor ESR, improving regulation accuracy at light loads.
No-R_SENSE current sensing	Uses MOSFET R_DS(on) instead of discrete sense resistors - reduces BOM cost and PCB area.
Selectable ultrasonic pulse skip	Maintains >33 kHz minimum switching frequency to eliminate audible noise in sensitive environments.
Soft output discharge	Actively discharges OUT1/OUT2 during shutdown - prevents floating outputs and ensures safe power-down sequencing.

Applications

FPGA Core & I/O Power

Industrial 24 V Embedded System

Use Scenario: Powering Xilinx Artix-7 FPGA with separate 1.0 V core and 1.8 V I/O rails from a 24 V supply.

IC Role / Device Role / Timing Role: Dual-channel buck controller regulating both rails; COT architecture ensures <50 µs recovery from 0→2 A load step on core rail.

Use Value: Eliminates need for external current-sense resistors and complex compensation networks, reducing solution size by >30 %.

Use Scenario: Distributed power in PLC backplane with 24 V input powering microcontroller (3.3 V), CAN transceiver (5 V), and analog sensors (2.5 V).

IC Role / Device Role / Timing Role: Primary DC-DC controller generating 3.3 V (OUT1) and 5 V (LDO5), with adjustable LDO supplying precision 2.5 V reference.

Use Value: Single-chip solution replaces three discrete regulators, enabling conformal coating and meeting IEC 61000-4-2 ESD immunity requirements.

Notebook Computer Subsystem

High-Density DC-DC Module

Use Scenario: Secondary power stage for USB-C PD negotiation IC and display backlight driver in thin-and-light notebook.

IC Role / Device Role / Timing Role: Supplies 3.3 V (OUT2) and 1.8 V (adjustable LDO) with soft-start and independent PGOOD for firmware-controlled power sequencing.

Use Value: 2 ms fixed soft-start prevents inrush into capacitive loads; PGOOD1/PGOOD2 enable BIOS-level rail validation before boot.

Use Scenario: 30 W, 1.5" × 1.5" quarter-brick module delivering 3.3 V/5 A and 1.2 V/10 A for telecom line card.

IC Role / Device Role / Timing Role: Controller IC managing dual-phase buck stages; VFQFPN-32 package enables bottom-side thermal transfer to heatsink.

Use Value: Exposed pad + low R_DS(on) gate drivers achieve >92 % efficiency at full load, meeting Level VI efficiency requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buck controller applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS546B24A	Dual-channel, single-die buck controller with PMBus interface; requires external current-sense resistors; no integrated LDOs.	Targets digitally controlled server VRMs; lacks analog LDOs and ripple-compensated integrator loop.	Choose for telemetry and dynamic voltage scaling; avoid if analog-only design or LDO integration is required.
ISL95831	Single-channel controller with integrated 5 V LDO; no second buck channel or adjustable LDO; uses voltage-mode control.	Suitable for single-rail notebook CPU cores; cannot replace dual-output requirement of PM6681A.	Only viable if redesigning to single-output topology; lacks OUT2 and LDO adjustability.

Compared with TPS546B24A and ISL95831, the PM6681A uniquely combines dual COT buck control, two integrated LDOs (one adjustable), and ripple-based compensation-making it optimal for space-constrained industrial and FPGA systems where analog simplicity and thermal efficiency are prioritized over digital control.

Availability

PM6681A is available at Aetrix Electronics and suitable for FPGA system power, industrial 24 V embedded systems, and high-density DC-DC modules requiring stable component supply, long-term lifecycle support, and consistent parametric performance across temperature.

Supply support for PM6681A includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in power management, microcontrollers, and analog ICs for industrial, automotive, and consumer markets.

The PM6681A belongs to ST's high-efficiency DC-DC controller product line, engineered specifically for multi-rail power delivery in space- and thermally constrained embedded systems where analog precision and minimal external components are critical.

FAQ

What is the purpose of the V5SW pin?

The V5SW pin controls the internal 5 V LDO5 regulator's operating mode. When connected to an external 5 V supply >4.9 V, LDO5 shuts down and the LDO5 output connects directly to that supply via a 3 Ω internal switch-improving efficiency at high load. When tied to GND, LDO5 remains active and supplies gate drivers and external loads.

How does the PM6681A achieve lossless current sensing?

It uses the R_DS(on) of the synchronous rectifier MOSFET as the current-sense element. The CSENSE1/2 pins monitor the voltage drop across the MOSFET's channel during conduction, eliminating the need for discrete sense resistors and associated power loss and board area.

Can the two buck channels operate at different switching frequencies?

Yes. The FSEL pin accepts three logic levels (GND, VREF, or LDO5) to configure three distinct frequency sets-each applied independently to OUT1 and OUT2 sections-enabling optimization for EMI reduction, efficiency, or thermal distribution in dual-rail designs.

What protection features are implemented in hardware?

Hardware-enforced protections include latched undervoltage lockout (UVP), non-latched overvoltage protection (OVP), thermal shutdown, negative current limit detection, and soft-output discharge. All operate autonomously without firmware or external supervision, ensuring fail-safe behavior during fault conditions.

PM6681A Specifications

Product attributes: Attribute value

Manufacturer:: STMicroelectronics

Series:: -

Package/Case:: 32-VFQFN Exposed Pad

Packaging:: Tray

Product Status:: Active

Topology:: Step-Down (Buck) (2), Linear (LDO) (2)

Number of Outputs:: 4

Frequency - Switching:: Down to 33kHz

Voltage/Current - Output 1:: 0.9V ~ 5V, 100mA

Voltage/Current - Output 2:: 0.9V ~ 3.3V, 100mA

Voltage/Current - Output 3:: 5V, 100mA

w/LED Driver:: No

w/Supervisor:: No

w/Sequencer:: No

Voltage - Supply:: 4.5V ~ 36V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 32-VFQFPN (5x5)

PM6681A FAQ

1.How can I place an order for PM6681A through Aetrix?

Please submit a Request for Quotation (RFQ) for PM6681A on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for PM6681A reliable?

The price and inventory of PM6681A are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PM6681A is usually 5 days.

3.What payment methods are accepted for PM6681A?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PM6681A transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for PM6681A?

PM6681A orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your PM6681A order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for PM6681A?

For technical support, including PM6681A datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PM6681A requirements.

6.How does Aetrix verify that PM6681A is sourced from the original manufacturer or authorized distributors?

All PM6681A products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PM6681A meets industry standards.

7.What is the process for return or replacement of PM6681A?

All PM6681A units undergo pre-shipment inspection (PSI). If there is an issue with PM6681A, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The PM6681A part is unused and in its original packaging.

Return procedure for PM6681A:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…