STMicroelectronics PM6686

Overview

PM6686 from STMicroelectronics is a dual synchronous step-down controller with integrated LDO and auxiliary charge pump monitor, designed for multi-rail notebook power systems. It delivers two independently programmable buck outputs (0.7–5.5 V / 0.7–2.5 V, ±1.5% accuracy), a 200 mA adjustable LDO (0.7–4.5 V), and supports constant-on-time control with selectable 33/150/300 kHz switching frequencies.

For engineers reviewing the PM6686 datasheet, PM6686 pinout, PM6686 application, or PM6686 equivalent, key selection criteria include lossless R_DS(on) current sensing, non-audible pulse-skip mode, independent EN/PG signals per channel, switchover-capable LDO, and VFQFPN-32 (5 × 5 mm) thermal performance in space-constrained mobile platforms.

Technical Context

The PM6686 implements a constant-on-time (COT) architecture with voltage feed-forward, enabling fast transient response (<5 µs load step recovery) and near-constant frequency operation across line/load variations. Each buck section uses low-side MOSFET R_DS(on) sensing for lossless current monitoring and features programmable overcurrent protection via ILIM1/ILIM2 pins.

It integrates three reference sources: 2.0 V (±1.0%, 50 µA), 3.3 V (±2.0%, 5 mA), and internal feedback paths for both buck sections and the LDO. The charge pump feedback (CP_FB) input enables closed-loop monitoring of external 14 V charge pumps used for high-side gate drive or auxiliary rails.

Key Specifications

Pinout & Package

PM6686 is housed in a thermally enhanced VFQFPN-32 (5 × 5 mm, 0.5 mm pitch) package with exposed thermal pad, optimized for high-power-density notebook VRMs. The 32-pin layout supports dual-channel gate drive, independent enable/power-good, precision references, and flexible feedback configuration.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buck controller applications.

Compared with RT8209MZQW and ISL95836IRZ, the PM6686 uniquely combines dual independent buck control, integrated switchover LDO, and non-audible pulse skip in a compact 5 × 5 mm package - making it the only solution that satisfies simultaneous requirements for notebook rail sequencing, acoustic noise compliance, and board-area reduction.

Availability

PM6686 is available at Aetrix Electronics and suitable for notebook computers, tablet PCs, and 3–4 cell Li+ battery-powered mobile devices requiring stable component supply, long-term lifecycle support, and qualified automotive-grade traceability.

Supply support for PM6686 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and analog ICs for automotive, industrial, and consumer applications.

The PM6686 belongs to ST's notebook-specific power controller product line, engineered to replace multi-IC power trees with single-chip solutions supporting DDR memory, chipset, GPU, and peripheral rail requirements.

FAQ

What is the maximum supported output current for each buck channel?

The PM6686 does not integrate power MOSFETs and is a controller-only device; maximum output current depends on external FET selection, inductor rating, and thermal design. With typical 3 mΩ high-side/low-side MOSFETs and 1.5 µH inductors, each channel supports up to 12 A continuous output current while maintaining <65°C junction temperature under 28 V input.

Can the LDO operate simultaneously with the buck outputs?

Yes - the LDO operates independently and can be enabled concurrently with either or both buck channels. Its output is regulated separately and may be configured as fixed 3.3 V/5 V or adjustable 0.7–4.5 V. When switchover is active, the LDO shuts down and routes LDO_SW voltage through an internal 0.8 Ω or 1.1 Ω switch.

How is sequencing between OUT1 and OUT2 implemented?

Sequencing is achieved by connecting EN1 to VREF2 to delay OUT1 startup until OUT2 reaches regulation, or by tying EN2 to VREF2 for reverse sequencing. VREF2 (2.0 V reference) provides a stable, low-current enable threshold that avoids dependency on output voltage ramp rates or external timers.

Does the PM6686 support I²C or SMBus communication?

No - the PM6686 is an analog-controlled controller with no digital interface. Output voltages are set via resistor dividers on FB1/FB2, frequency via TON pin logic levels, and operating modes (PWM/SKIP) via SKIP pin. All configuration is hardware-based with no firmware or serial bus required.