STMicroelectronics PM6686TR

Overview

PM6686TR from STMicroelectronics is a dual synchronous step-down controller with integrated LDO and auxiliary charge pump monitor, designed for multi-rail notebook power systems. It delivers two independently regulated outputs (OUT1: 0.7–5.5 V; OUT2: 0.7–2.5 V) with ±1.5% valley regulation accuracy, constant-on-time control, and selectable 33/150/300 kHz switching frequencies. Its lossless R_DS(on) current sensing enables precise programmable current limiting for DDR1/2/3 and chipset rails.

For engineers reviewing the PM6686TR datasheet, PM6686TR pinout, PM6686TR application, or PM6686TR equivalent, key selection criteria include dual adjustable output voltage programming, switchover-capable 200 mA LDO, non-audible pulse-skip mode, and VFQFPN-32 package thermal performance in space-constrained mobile platforms.

Technical Context

The PM6686TR implements constant-on-time (COT) control with voltage feed-forward to maintain near-constant frequency across line/load variations while delivering fast transient response. Each buck section features independent enable (EN1/EN2), power-good (PG1/PG2), and feedback (FB1/FB2) pins, supporting sequencing and fault isolation in multi-rail systems.

It integrates a 200 mA switchover LDO with fixed 3.3 V/5.0 V or adjustable 0.7–4.5 V output, plus a dedicated CP_FB input to monitor external charge pump voltage and trigger no-audible SKIP cycles. The device supports three selectable switching frequencies via TON pin and includes latched OVP/UVP protection per rail.

Key Specifications

Pinout & Package

PM6686TR is housed in a thermally enhanced VFQFPN-32 (5 × 5 mm, 0.5 mm pitch) package with exposed thermal pad, optimized for high-power-density notebook DC/DC designs.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-buck controller with integrated LDO applications.

Compared with RT8205AZSP and ISL95831IRZ, the PM6686TR uniquely balances adjustability (0.7–5.5 V outputs), integrated switchover LDO, and charge pump monitoring in a compact 5 × 5 mm package-making it optimal for cost-sensitive, space-constrained notebook and tablet power architectures where full IMVP compliance is not required.

Availability

PM6686TR is available at Aetrix Electronics and suitable for notebook computers, DDR memory power systems, and mobile PDA power management requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for PM6686TR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in power management, microcontrollers, and analog ICs for automotive, industrial, and consumer applications.

The PM6686TR belongs to ST's notebook power controller product line, engineered specifically for high-efficiency, multi-rail DC/DC conversion in portable computing platforms with stringent thermal and footprint constraints.

FAQ

What is the function of the TON pin on the PM6686TR?

The TON pin selects one of three switching frequencies: 33 kHz (for low-noise operation), 150 kHz (balanced efficiency/size), or 300 kHz (compact magnetics). It sets the on-time for both buck sections simultaneously using an external resistor to GND, enabling optimization for acoustic noise, efficiency, or board area.

How does the LDO switchover function operate?

When LDOREFIN is tied to GND or VCC (selecting 5 V or 3.3 V fixed output), the LDO monitors LDO_SW. If LDO_SW voltage is within ±5% of the selected LDO output, the internal regulator shuts down and a 0.8 Ω (5 V) or 1.1 Ω (3.3 V) switch connects LDO to LDO_SW, sourcing up to 200 mA from the external rail.

Can the PM6686TR regulate both outputs at adjustable voltages simultaneously?

Yes - FB1 and FB2 can each be connected to resistive dividers from OUT1 and OUT2 to GND, enabling independent adjustment from 0.7 V to 5.5 V (OUT1) and 0.7 V to 2.5 V (OUT2) with ±1.5% valley regulation accuracy, supported by separate current sensing and soft-start circuits.

What protection features are implemented per buck section?

Each buck section includes latched overvoltage protection (OVP), undervoltage protection (UVP), and independent power-good (PG1/PG2) monitoring with asymmetric tolerance windows (±10% for OUT1; +14%/−10% for OUT2). Thermal shutdown and current-limit fault handling are also fully isolated per channel.