NXP Semiconductors PM823HN/A0CHP

Overview

PM823HN/A0CHP from NXP Semiconductors is a dual synchronous buck regulator with integrated 525 mA LDO, configured for 1.1 V / 2.2 V / 1.8 V fixed outputs in the 24-pin QFN package. It delivers 1.5 A per buck channel at 3 MHz switching frequency, supports DVS/AVS control via two digital inputs, and features ultra-low 15 µA sleep current - enabling compact, thermally efficient power management in Wi-Fi modules and smart home hubs.

For engineers reviewing the PM823HN/A0CHP datasheet, PM823HN/A0CHP pinout, PM823HN/A0CHP application, or PM823HN/A0CHP equivalent, this device is selected for its QFN-24 footprint with dedicated PG1/PG2/PGLDO outputs, programmable operating modes (Active/Sleep), and support for both serial interface programming and hardware-based dynamic voltage scaling in space-constrained IoT systems.

Technical Context

The PM823HN/A0CHP implements two independent PWM-controlled synchronous buck regulators with internal compensation and a separate LDO powered from either PVIN or buck output (≥1.6 V). Its 3 MHz fixed-frequency operation enables small external LC components, while the proprietary 1-wire serial interface (enabled when DVS1 = high) allows runtime voltage reconfiguration without additional I²C/SPI lines.

Power sequencing is enforced in QFN variants: Buck2 powers up first, followed by the LDO, then Buck1 - controlled via shared EN1/EN2/ENLDO logic. All three regulators support independent enable/disable via dedicated input pins, and each includes open-drain power-good monitoring with 95% VOUT rising threshold and 5% hysteresis.

Key Specifications

Pinout & Package

PM823HN/A0CHP uses the 24-pin QFN package (4 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad (EPAD) connected to system ground. Pin functions are validated per NXP Rev. 5 datasheet Figure 5 and Table 3.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail PMIC applications.

Compared with MPQ4572GQ-AEC1-P and TPS65023BRSBR, PM823HN/A0CHP uniquely integrates dual 1.5 A bucks + 525 mA LDO in QFN-24 with hardware DVS and 15 µA sleep current - making it optimal for cost- and space-sensitive Wi-Fi module designs requiring exactly three tightly regulated rails.

Availability

PM823HN/A0CHP is available at Aetrix Electronics and suitable for Wi-Fi modules, smart home hubs, and IoT edge gateways requiring stable component supply, long-term lifecycle assurance, and consistent QFN-24 packaging for automated assembly.

Supply support for PM823HN/A0CHP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in power management ICs for wireless infrastructure.

The PM823HN/A0CHP belongs to NXP's PM8xx family of highly integrated power management ICs designed specifically for Marvell Wi-Fi/BT system-on-modules - emphasizing minimal footprint, low quiescent current, and hardware-controlled dynamic voltage scaling.

FAQ

What output voltages does the PM823HN/A0CHP deliver?

The PM823HN/A0CHP is factory-configured to deliver fixed output voltages of 1.1 V (Buck1), 2.2 V (Buck2), and 1.8 V (LDO), as specified in Table 1 of the NXP datasheet Rev. 5. These values are laser-trimmed during production and cannot be altered via the serial interface - unlike programmable variants such as PM823UK/A0CZ. The PM823HN/A0CHP maintains ±2% DC accuracy across load, line, and temperature conditions.

Does the PM823HN/A0CHP support independent enable control for each regulator?

Yes, the PM823HN/A0CHP provides dedicated enable inputs EN1 (Buck1), EN2 (Buck2), and ENLDO (LDO) in its QFN-24 package. However, per Section 5.4 of the datasheet, these pins must be tied together for standard power-up sequencing (Buck2 → LDO → Buck1). Independent control is possible only in variants without enforced sequencing - but the PM823HN/A0CHP is explicitly designated as a QFN part with power sequence, so individual enable functionality is not supported in normal operation.

What is the purpose of the DVS0/SDI and DVS1 pins on the PM823HN/A0CHP?

On the PM823HN/A0CHP, DVS1 selects operating mode (Active/Sleep), while DVS0/SDI serves dual roles: as DVS0 when DVS1 = low, or as serial data input (SDI) when DVS1 = high. This enables hardware-based dynamic voltage scaling without software overhead, or runtime voltage reprogramming via the proprietary 1-wire interface. Both pins must be terminated - floating is prohibited per datasheet Table 3.

How does the PM823HN/A0CHP handle thermal management in high-power operation?

The PM823HN/A0CHP uses a thermally enhanced QFN-24 package with an exposed EPAD connected to system ground, achieving 50 °C/W junction-to-ambient thermal resistance. Internal over-temperature shutdown triggers at 145 °C with 20 °C hysteresis. To maintain full 1.5 A output current at 85 °C ambient, the EPAD must be soldered to a ≥200 mm² copper pour with ≥4 thermal vias to inner ground layers - as validated in NXP's layout guidelines (Section 8.1).

Can the PM823HN/A0CHP be used with input sources below 2.7 V?

No - the absolute minimum PVIN voltage for the PM823HN/A0CHP is 2.7 V, as defined in Table 5 (Recommended Operating Conditions). Below this, UVLO activates at 2.35 V (Table 7), disabling all regulators. While the LDO can accept VINLDO as low as 1.6 V, it must be powered from a valid buck output (≥1.6 V) or external source within 2.7–5.5 V. Operation below 2.7 V violates absolute maximum ratings and risks functional failure.