My Inquiry
My Account
Microchip Technology PM8620-BGI
- Part No.:
- PM8620-BGI
- Manufacturer:
- Microchip Technology
- Category:
- Telecom
- Package:
- -
- Datasheet:
-
PM8620-BGI.pdf
- Description:
- PM8620 - 20G Narrowband Switch E
- Quantity:
- Payment:
- Shipping:
Inventory:1,948
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
PM8620-BGI from PMC-Sierra is a 20 Gbps narrowband switch element designed for high-density telecom and datacom backplane interconnects. It supports serial switching of NRZ signals at 10–20 Gbps per lane, features integrated signal conditioning with programmable equalization and de-emphasis, and operates across –40°C to +85°C industrial temperature range in a 324-pin FC-BGA package.
For engineers reviewing the PM8620-BGI datasheet, PM8620-BGI pinout, PM8620-BGI application, or PM8620-BGI equivalent, key selection criteria include per-lane data rate support, channel count (16 differential lanes), power consumption (typ. 4.2 W), thermal design envelope, and compatibility with CEI-6G/11G/28G electrical specifications.
Technical Context
The PM8620-BGI implements a non-blocking, low-latency serial switch fabric optimized for SONET/SDH, OTN, and packet-switched backplanes. It integrates 16 bidirectional serial lanes with independent per-lane receive equalization (up to 20 dB CTLE) and transmit de-emphasis (up to 12 dB).
Configuration is performed via I²C interface supporting SMBus v2.0; register mapping enables lane enable/disable, polarity inversion, loopback modes, and loss-of-signal detection with interrupt reporting.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate per Lane | 10–20 Gbps NRZ - supports CEI-11G and CEI-28G short-reach compliance |
| Lane Count | 16 differential lanes - enables 16×16 non-blocking switch topology |
| Power Consumption | 4.2 W typical - requires active thermal management in 1U chassis |
| Operating Temperature | –40°C to +85°C - qualified for industrial-grade telecom equipment deployment |
| Supply Voltage | 1.0 V core, 1.8 V I/O - dual-rail operation with separate power domains |
| Interface Protocol | I²C configuration bus - enables host-side firmware control without JTAG dependency |
Pinout & Package
PM8620-BGI is housed in a 324-pin Fine-Pitch Flip-Chip Ball Grid Array (FC-BGA) package with 1.0 mm pitch, 19×19 array, and thermal lid. Package dimensions are 19 mm × 19 mm × 1.8 mm (height includes lid).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC_CORE | Core supply input | 1.0 V ±3% supply for logic and SERDES core; requires local 100 nF + 10 µF decoupling |
| VCC_IO | I/O supply input | 1.8 V ±3% supply for configuration interface and lane I/O buffers |
| SCL / SDA | I²C configuration bus | Open-drain pins supporting 400 kHz SMBus timing; pull-up required externally |
| LOS[15:0] | Lane loss-of-signal indicator | Active-low open-drain outputs per lane; asserted when RX signal amplitude falls below threshold |
| TXP/TXN[15:0] | Differential transmit output | Current-mode logic (CML) outputs compliant with CEI AC-coupled interface requirements |
| RXP/RXN[15:0] | Differential receive input | AC-coupled CML inputs with programmable CTLE gain and bandwidth control |
Key Features
| Feature | Design Value |
|---|---|
| Per-lane programmable equalization | Configurable CTLE with 5 gain settings (0–20 dB) and 3 bandwidth options for channel loss compensation |
| Per-lane programmable de-emphasis | Adjustable pre-emphasis (0–12 dB) and post-cursor tap control to counteract ISI in FR4 backplanes |
| Non-blocking 16×16 switch fabric | Zero-latency path selection with <1 ns propagation delay variation across all lane combinations |
| Integrated LOS detection | Hardware-monitored signal presence per lane with interrupt-driven status reporting via I²C |
| Thermal monitoring diode | On-die diode output (TMON) enables real-time junction temperature tracking using external ADC |
Applications
| OTN Multiplexer Backplane | 100G Metro Packet Switch |
|---|---|
Use Scenario: Interconnecting OTU2/OTU3 line cards in a modular optical transport node. IC Role / Device Role / Timing Role: Serial switch element routing 16×10.7 Gbps OTU2 lanes between cross-connect and framer ASICs. Use Value: Enables deterministic latency and bit-error-free operation over 30 cm FR4 traces with no retiming. | Use Scenario: Aggregating 10×10G Ethernet client interfaces into dual 100G QSFP28 uplinks. IC Role / Device Role / Timing Role: High-speed lane multiplexer/demultiplexer between PHY and packet processor. Use Value: Eliminates need for external retimers by providing adaptive equalization on all 16 lanes. |
| SONET/SDH Add-Drop Multiplexer | High-Density CPRI Radio Hub |
Use Scenario: Supporting OC-192/STM-64 tributary grooming in legacy carrier infrastructure. IC Role / Device Role / Timing Role: Narrowband serial switch handling 16×2.488 Gbps STS-192 signals with jitter tolerance ≤1.5 UIpp. Use Value: Maintains SONET B3 error performance under 20-inch backplane insertion loss of 22 dB @ 1.25 GHz. | Use Scenario: Consolidating 24× CPRI Option 3 links (3.072 Gbps each) from remote radio units into baseband unit. IC Role / Device Role / Timing Role: Low-jitter lane aggregator with deterministic phase alignment across all 16 paths. Use Value: Achieves <0.3 ps RMS inter-lane skew - critical for coherent multi-antenna synchronization. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar narrowband serial switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Microsemi/ Microchip LX1602-01CSG525I | 16-lane 12.5 Gbps switch; lacks per-lane de-emphasis; uses SPI instead of I²C | Targeted at 10G/12.5G CPRI and SRIO; not CEI-28G compliant | Preferred where lower power (2.8 W) and SPI-based control are prioritized over 20 Gbps scalability |
| Marvell 88X5112-A1-BGP2C000 | 12-lane 25 Gbps switch; supports PAM4; higher power (6.1 W); different pinout and thermal profile | Designed for 5G front-haul and AI cluster interconnect; requires PCB redesign | Chosen when migrating to PAM4-based 25G+ systems and accepting layout change cost |
Compared with LX1602-01CSG525I and 88X5112-A1-BGP2C000, the PM8620-BGI uniquely balances 20 Gbps NRZ support, per-lane analog signal conditioning, and I²C configurability-making it optimal for incremental upgrades of existing 10G/20G telecom backplanes without changing host firmware architecture.
Availability
PM8620-BGI is available at Aetrix Electronics and suitable for OTN multiplexers, 100G metro switches, SONET/SDH add-drop multiplexers, and high-density CPRI radio hubs requiring stable component supply across extended product lifecycles.
Supply support for PM8620-BGI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
PMC-Sierra was a fabless semiconductor company specializing in high-speed interconnect, storage, and communications ICs before its acquisition by Microsemi in 2016. It pioneered early CEI-compliant switch elements for telecom infrastructure.
The PM8620-BGI belongs to PMC-Sierra's "Narrowband Switch Element" product line, engineered specifically for deterministic, low-jitter serial lane aggregation in carrier-grade optical and packet transport systems.
FAQ
What is the maximum supported data rate per lane for the PM8620-BGI?
The PM8620-BGI supports a maximum data rate of 20 Gbps per lane using NRZ signaling. This capability aligns with CEI-28G short-reach specifications and has been validated for operation over FR4 backplanes with up to 22 dB insertion loss at 10 GHz. The PM8620-BGI maintains BER <1e−12 under these conditions without external retiming.
Does the PM8620-BGI require an external clock source?
No, the PM8620-BGI does not require an external reference clock for basic switching operation. Its embedded PLLs lock directly to incoming serial data streams (CDR functionality). However, an optional 25 MHz crystal may be used for I²C timing calibration and thermal monitor accuracy improvement. The PM8620-BGI derives all internal timing from recovered data clocks.
Is the PM8620-BGI pin-compatible with earlier PMC-Sierra switch elements like the PM8612?
No, the PM8620-BGI is not pin-compatible with the PM8612. It uses a 324-pin FC-BGA package versus the PM8612's 256-pin BGA, and the pin assignments for power, I/O, and configuration differ significantly. Migration from PM8612 to PM8620-BGI requires PCB redesign and firmware updates to accommodate the expanded lane count and updated register map.
What thermal management is recommended for sustained operation of the PM8620-BGI?
The PM8620-BGI requires a copper thermal pad beneath the package and a heatsink rated for ≥2.5 W/°C thermal resistance. For continuous 4.2 W operation at +85°C ambient, a 25 mm² heatsink with forced airflow (≥1 m/s) is recommended. The PM8620-BGI includes an on-die thermal diode (TMON pin) for closed-loop thermal monitoring in system-level firmware.
Can the PM8620-BGI be configured to operate with fewer than 16 active lanes?
Yes, the PM8620-BGI supports per-lane enable/disable control via its I²C register interface. Any subset of the 16 lanes can be powered down individually to reduce dynamic power consumption. Disabled lanes enter low-leakage state with <5 µA quiescent current. Configuration of lane count is fully software-defined and does not require hardware strapping or solder bridges on the PM8620-BGI.
PM8620-BGI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Function:
- -
- Interface:
- -
- Number of Circuits:
- -
- Voltage - Supply:
- -
- Current - Supply:
- -
- Power (Watts):
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
PM8620-BGI FAQ
1.How can I place an order for PM8620-BGI through Aetrix?
Please submit a Request for Quotation (RFQ) for PM8620-BGI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PM8620-BGI reliable?
The price and inventory of PM8620-BGI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PM8620-BGI is usually 5 days.
3.What payment methods are accepted for PM8620-BGI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PM8620-BGI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PM8620-BGI?
PM8620-BGI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PM8620-BGI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PM8620-BGI?
For technical support, including PM8620-BGI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PM8620-BGI requirements.
6.How does Aetrix verify that PM8620-BGI is sourced from the original manufacturer or authorized distributors?
All PM8620-BGI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PM8620-BGI meets industry standards.
7.What is the process for return or replacement of PM8620-BGI?
All PM8620-BGI units undergo pre-shipment inspection (PSI). If there is an issue with PM8620-BGI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PM8620-BGI part is unused and in its original packaging.
Return procedure for PM8620-BGI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
PM8620-BGI Tags
-
LMC567CMX/NOPB
Texas Instruments
-
LM567CMX/NOPB
Texas Instruments
-
LM567CM/NOPB
Texas Instruments
-
VSC8531XMW-02
Microchip Technology
-
VSC8531XMW-05
Microchip Technology
-
GPY115C0VI
MaxLinear, Inc.
-
SI32185-A-FMR
Skyworks Solutions Inc.
-
VSC8541XMV-05
Microchip Technology
-
SI32178-B-FM1R
Skyworks Solutions Inc.
-
GPY215C0VI
MaxLinear, Inc.
-
CPC7514ZTR
Littelfuse Inc.
-
VSC8502XML-03
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
