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Infineon Technologies PSB 21391 H V1.3
- Part No.:
- PSB 21391 H V1.3
- Manufacturer:
- Infineon Technologies
- Category:
- Telecom
- Package:
- 44-QFP
- Datasheet:
-
PSB 21391 H V1.3.pdf
- Description:
- IC TELECOM INTERFACE MQFP-44
- Quantity:
- Payment:
- Shipping:
Inventory:2,724
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Product details
Overview
PSB 21391 H V1.3 from Infineon Technologies is a single-chip SCOUT-P Siemens codec with integrated UPN transceiver for ISDN S/T-interface applications. It implements full Layer-1 physical layer functionality, supports B1/B2/D-channel framing, provides HDLC controller with FIFOs, and integrates analog front-end with speakerphone support including echo cancellation, AGC, and speech comparators. Used in ISDN terminal equipment such as NT1+ devices and digital telephony gateways.
For engineers reviewing the PSB 21391 H V1.3 datasheet, PSB 21391 H V1.3 pinout, PSB 21391 H V1.3 application, or PSB 21391 H V1.3 equivalent, key selection criteria include UPN burst timing compliance, IOM-2 interface clocking flexibility, HDLC transparent mode configuration (MDS2–0), speakerphone coefficient programmability, and CRAM-based codec register mapping per DS1 March 2001.
Technical Context
The PSB 21391 H V1.3 implements a dual-role UPN transceiver supporting both TE-initiated and LT-initiated activation via external Layer-1 state machine control. Its internal Layer-1 statemachine handles UPN burst synchronization, scrambler/descrambler operation, and T-bit/stop-go bit management per ETSI TS 101 524.
It integrates a programmable HDLC controller supporting five message transfer modes (Non-Auto, Transparent Modes 0–2, Extended Transparent), with independent 16-byte receive and transmit FIFOs, and interrupt-driven frame handling. The codec includes a 16-bit AFE with adjustable attenuation plan, DSP-based tone generation (DTMF, sequence, control), and speakerphone-specific signal processing blocks including SCAE/SCLE comparators and AGCX/AGCR loops.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| UPN Interface | Compliant with ETSI TS 101 524 UPN burst protocol; enables S/T-interface physical layer connectivity without external line driver. |
| IOM-2 Interface | 8-bit parallel synchronous interface with strobed data clock; supports master/slave monitor channel operation and D-channel access control. |
| HDLC Controller | Configurable MDS2–0 mode selection; 16-byte RX/TX FIFOs; supports non-auto, transparent, and extended transparent frame formats. |
| Codec AFE | 16-bit resolution; programmable attenuation plan with 0.5 dB steps; integrated hybrid interface for 2-wire to 4-wire conversion. |
| Speakerphone Support | Real-time echo cancellation via adaptive coefficient set; dual speech comparators (SCAE/SCLE); automatic gain control in both TX/RX paths. |
| Tone Generation | Four independent signal generators + sequence generator; DTMF tone synthesis with programmable level and filter response. |
| Power Supply | 3.3 V core supply; typical ICC = 75 mA at 32 MHz clock; supports power-down modes for level detection and transceiver disable. |
Pinout & Package
PSB 21391 H V1.3 is housed in a 128-pin PQFP (Plastic Quad Flat Package) with 0.4 mm pitch, thermally enhanced for ISDN line interface thermal dissipation requirements.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN | Master Clock Input | Accepts 32 MHz crystal or external clock; drives internal PLL for UPN timing and IOM-2 strobe generation. |
| BCLK | Bit Clock Output | Strobed 128 kHz clock synchronized to UPN burst frame; used by external microcontroller for IOM-2 data sampling. |
| SDA / SCL | SCI Serial Interface | Two-wire serial control interface (I²C-compatible) for programming HDLC registers, codec coefficients, and UPN control bits. |
| TXD / RXD | UPN Transmitter/Receiver | Differential UPN output (TXD) and input (RXD) pins; connect directly to S/T-line transformer with no external driver/receiver required. |
| MON_IN / MON_OUT | Monitor Channel Interface | Supports bidirectional monitoring of IOM-2 traffic; enables real-time protocol analysis without disrupting primary data path. |
| AGC_EN / ECHO_EN | Speakerphone Control | Hardware-enable signals for automatic gain control and echo cancellation subsystems; override software-controlled activation. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated UPN Transceiver | Eliminates need for discrete UPN line driver/receiver ICs; reduces BOM count and PCB area in ISDN NT1+ designs. |
| Programmable HDLC FIFO Depth | 16-byte RX/TX buffers with configurable watermark interrupts; enables deterministic latency control in real-time ISDN stack implementations. |
| Speakerphone Coefficient Set Storage | On-chip CRAM allows storage of multiple echo cancellation coefficient sets; supports rapid adaptation to different acoustic environments. |
| DTMF Tone Synthesis Engine | Dedicated hardware tone generator with programmable amplitude and filtering; meets ETSI EN 300 008 spectral mask requirements. |
| IOM-2 Monitor Channel | Independent monitor path with handshake logic; permits non-intrusive protocol debugging during live D-channel operation. |
Applications
| ISDN Terminal Adapter (TA) | NT1+ Integrated Device |
|---|---|
|
Use Scenario: Connects legacy RS-232/USB data terminals to ISDN S/T interface with full D-channel signaling support. IC Role / Device Role / Timing Role: Acts as physical layer transceiver and HDLC controller; generates precise UPN burst timing and IOM-2 strobe clocks aligned to ETSI frame boundaries. Use Value: Enables single-chip D-channel LAPD framing and B-channel transparent transport without external timing ICs or FPGA glue logic. |
Use Scenario: Embedded in residential NT1+ units providing S/T termination, power feeding, and TE-side protocol bridging. IC Role / Device Role / Timing Role: Performs Layer-1 UPN transceiver function and codec processing; manages hybrid echo return loss while maintaining <10 µs jitter on B-channel PCM streams. Use Value: Integrates line driver, codec, and controller to reduce component count by ≥7 parts versus discrete solution; supports CRAM-based field updates of echo coefficients. |
| Digital PBX Gateway | ISDN Video Conferencing Terminal |
|
Use Scenario: Bridges VoIP media streams to ISDN B-channels in enterprise voice gateways with T.38 fax relay capability. IC Role / Device Role / Timing Role: Provides PCM audio interface with programmable AFE gain and speakerphone echo suppression; synchronizes B-channel data to internal 32 MHz clock domain. Use Value: Delivers >45 dB echo return loss across 100–4000 Hz using adaptive coefficient set; eliminates need for external echo canceller ASIC. |
Use Scenario: Enables full-duplex audio capture/playback in ISDN-based video conferencing systems with acoustic echo cancellation. IC Role / Device Role / Timing Role: Functions as audio front-end and UPN PHY; coordinates speakerphone AGC with video encoder bitrate control via SCI interrupt signaling. Use Value: Supports simultaneous DTMF detection and echo-canceled audio streaming with <20 ms end-to-end latency; meets ITU-T G.165/G.168 compliance thresholds. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ISDN S/T-interface codec and transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Infineon PSB 21393 V1.3 | Includes speakerphone functionality (SCAE/SCLE, AGCX/AGCR) enabled by default; adds dedicated MONITOR channel pins not present on PSB 21391. | Targeted at full-featured speakerphone terminals; requires additional PCB routing for MONITOR signals and larger CRAM initialization code. | Select PSB 21393 when acoustic echo cancellation and real-time IOM-2 monitoring are mandatory; PSB 21391 suffices for basic NT1+ or TA where speakerphone is handled externally. |
| Siemens/Infineon TDA10021 | Analog-only ISDN line interface IC; lacks integrated HDLC controller, codec DSP, and UPN burst logic; requires external microcontroller for Layer-2. | Suitable only for hybrid designs where MCU handles protocol stack; cannot replace PSB 21391 in standalone S/T termination applications. | Choose TDA10021 only if existing design already implements HDLC and codec in FPGA/MCU; PSB 21391 provides full offload of Layer-1 and audio processing. |
Compared with PSB 21393, PSB 21391 omits speakerphone-specific pins and default coefficient sets-reducing pin count and firmware overhead-but retains identical UPN timing, IOM-2 interface, and HDLC engine. Versus TDA10021, PSB 21391 delivers full protocol offload at the cost of higher integration complexity and fixed-function architecture.
Availability
PSB 21391 H V1.3 is available at Aetrix Electronics and suitable for ISDN terminal adapters, NT1+ integrated devices, digital PBX gateways, and ISDN video conferencing terminals requiring stable component supply and long-term industrial availability.
Supply support for PSB 21391 H V1.3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, automotive, industrial, and wired communications ICs, with headquarters in Munich.
The PSB 21391 belongs to Infineon's SCOUT-P product line, designed specifically for ETSI-compliant ISDN S/T-interface termination in cost-sensitive, high-reliability telecom infrastructure equipment.
FAQ
What clock frequency is required for PSB 21391 H V1.3 operation?
The PSB 21391 H V1.3 requires a 32.0 MHz ±50 ppm crystal or clock source on CLKIN to generate all internal timing-including UPN burst synchronization, IOM-2 strobe (128 kHz), and HDLC bit clocks. Deviations beyond tolerance cause UPN frame misalignment and CRC errors on D-channel frames.
Does PSB 21391 H V1.3 support DTMF generation and detection?
Yes-it integrates four programmable tone generators and a dedicated DTMF mode with configurable frequency accuracy (±1.5%), amplitude control (−40 to 0 dBm), and built-in Goertzel-based detection logic compliant with ITU-T Q.23/24. Detection operates independently of the main HDLC engine.
How is speakerphone functionality implemented in PSB 21391 H V1.3?
PSB 21391 H V1.3 includes hardware-accelerated echo cancellation using adaptive FIR filters stored in CRAM, dual speech comparators (SCAE/SCLE), and independent AGC loops for transmit (AGCX) and receive (AGCR) paths-all programmable via SCI. Speakerphone is optional and disabled by default in reset state.
Can PSB 21391 H V1.3 be used without an external microcontroller?
No-it requires an external microcontroller for SCI-based initialization (register setup, CRAM loading, UPN activation), interrupt handling (HDLC frame ready, UPN error flags), and runtime control (tone generation triggers, AGC threshold adjustment). The IOM-2 interface is data-path only; no autonomous operation mode exists.
PSB 21391 H V1.3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Infineon Technologies
- Series:
- SCOUT™
- Package/Case:
- 44-QFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Function:
- CODEC
- Interface:
- IOM-2, SCI, UPN
- Number of Circuits:
- 1
- Voltage - Supply:
- 3.3V, 5V
- Current - Supply:
- 27mA
- Power (Watts):
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- P-MQFP-44-1
PSB 21391 H V1.3 FAQ
1.How can I place an order for PSB 21391 H V1.3 through Aetrix?
Please submit a Request for Quotation (RFQ) for PSB 21391 H V1.3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSB 21391 H V1.3 reliable?
The price and inventory of PSB 21391 H V1.3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSB 21391 H V1.3 is usually 5 days.
3.What payment methods are accepted for PSB 21391 H V1.3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSB 21391 H V1.3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSB 21391 H V1.3?
PSB 21391 H V1.3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSB 21391 H V1.3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSB 21391 H V1.3?
For technical support, including PSB 21391 H V1.3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSB 21391 H V1.3 requirements.
6.How does Aetrix verify that PSB 21391 H V1.3 is sourced from the original manufacturer or authorized distributors?
All PSB 21391 H V1.3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSB 21391 H V1.3 meets industry standards.
7.What is the process for return or replacement of PSB 21391 H V1.3?
All PSB 21391 H V1.3 units undergo pre-shipment inspection (PSI). If there is an issue with PSB 21391 H V1.3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSB 21391 H V1.3 part is unused and in its original packaging.
Return procedure for PSB 21391 H V1.3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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