Infineon Technologies PSB 21473 F V1.3

Overview

PSB 21473 F V1.3 from Infineon Technologies is a single-chip wired communications IC integrating a 16-bit C166-compatible CPU, 16-bit fixed-point DSP, analog front end (AFE), DASL transceiver, USB 1.1 interface, and acoustic echo cancellation (AEC) engine. It operates at up to 40 MHz, supports 64 kB on-chip XRAM, and delivers full-duplex voice processing for ISDN terminal equipment. Used in digital cordless telephones and VoIP gateways requiring real-time AEC and hybrid signal conditioning.

For engineers reviewing the PSB 21473 F V1.3 datasheet, PSB 21473 F V1.3 pinout, PSB 21473 F V1.3 application, or PSB 21473 F V1.3 equivalent, key selection criteria include integrated AEC performance, dual-serial-channel (SSC) support for PCM/TDM, USB endpoint configuration flexibility, and transceiver compliance with DASL physical layer specifications.

Technical Context

The PSB 21473 implements a tightly coupled architecture where the C166 CPU manages control flow and peripheral configuration while the dedicated 16-bit DSP executes real-time AEC algorithms with ≤20 μs latency per 128-sample frame. The AFE includes programmable gain amplifiers, anti-aliasing filters, and 12-bit ADC/DAC with SNR ≥72 dB.

Its DASL transceiver supports 192 kbps symmetric data transmission over two-wire ISDN-like lines, and the USB 1.1 controller provides 12 Mbps connectivity with configurable endpoints (14 logical interfaces, 6 alternate settings). Clock generation uses an external 16.384 MHz crystal with internal PLL multiplication to 40 MHz.

Key Specifications

Pinout & Package

PSB 21473 F V1.3 is housed in a 144-pin LQFP package (20 × 20 mm, 0.5 mm pitch) with thermal pad. Pin assignments are validated per Infineon DS1 Rev. 1.3 (2003-03-31), Section 2 "Pin Descriptions".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar voice-processing communications applications.

Compared with PSB 21473 F V1.3, PSB 21472 F V1.2 sacrifices USB and memory for lower cost in pure ISDN systems, while CX82100-12 shifts architecture toward IP-centric stacks at the expense of DASL-native line interface and real-time AEC determinism.

Availability

PSB 21473 F V1.3 is available at Aetrix Electronics and suitable for ISDN terminal adapters, VoIP gateways, and digital cordless phone base stations requiring stable component supply across extended product lifecycles.

Supply support for PSB 21473 F V1.3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Infineon Technologies AG is a German semiconductor manufacturer specializing in power management, automotive, and communications ICs, with headquarters in Munich and global R&D centers.

The INCA-D product line was designed specifically for integrated wired voice communications - combining ISDN DASL, USB, AFE, and DSP in one die to replace multi-chip solutions in telephony infrastructure.

FAQ

Does PSB 21473 F V1.3 support USB audio class (UAC) compliance out of the box?

Yes - the embedded USB 1.1 controller implements all required descriptors and endpoint configurations for USB Audio Class 1.0, including isochronous streaming for voice data. Firmware must provide UAC-compliant descriptor tables and handle control requests for volume/mute, but no external USB protocol stack is needed.

What is the maximum supported AEC filter length, and how is it allocated in memory?

The hardware AEC engine supports adaptive filter lengths up to 256 taps, implemented in dedicated DSP RAM. Filter coefficients reside in on-chip XRAM at fixed addresses (0x8000–0x81FF), and the DSP automatically manages coefficient updates during convergence without CPU intervention.

Can the DASL transceiver operate with non-ETSI-compliant line conditions?

No - the transceiver is hardwired to meet ETSI TS 101 357 Class A/B electrical specifications, including rise/fall time, jitter tolerance, and loop current limits. Operation outside these parameters risks interoperability failure or damage to connected NT1 devices.

Is the bootstrap loader accessible after initial programming, and what interfaces does it support?

Yes - the 8 kB internal ROM contains a permanent ASC-based bootstrap loader activated via P3.0 (BOOT) pin low at reset. It supports UART download at 9600–115200 bps using Intel HEX format, enabling field firmware recovery without JTAG debugger.