STMicroelectronics PSD4235G2-90U
- Part No.:
- PSD4235G2-90U
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 80-LQFP
- Datasheet:
-
PSD4235G2-90U.pdf
- Description:
- IC PROG PERIPH IC 80LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:2,385
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Product details
Overview
PSD4235G2-90U from STMicroelectronics is a Flash-based programmable system device (PSD) integrating dual-bank Flash memory (4 Mbit primary + 256 Kbit secondary), 64 Kbit SRAM, CPLD/DPLD logic (3000+ gates), and 7 configurable I/O ports (52 pins) for 16-bit MCU systems operating at 5 V. It supports concurrent read/erase/write operations and in-system programming via JTAG.
For engineers reviewing the PSD4235G2-90U datasheet, PSD4235G2-90U pinout, PSD4235G2-90U application, or PSD4235G2-90U equivalent, key selection criteria include dual-bank Flash concurrency, PLD-based chip select decoding, page register–enabled address expansion, and JTAG ISP capability for embedded 16-bit microcontroller platforms.
Technical Context
The PSD4235G2-90U implements a unified architecture where Flash memory, SRAM, and PLD logic are tightly coupled to an MCU bus interface supporting multiplexed and non-multiplexed 8/16-bit buses (e.g., 80C196, MC683xx, 80C51XA). Its dual-bank Flash enables real-time firmware updates without halting execution.
Its PLD subsystem comprises two distinct blocks: a 16-output macrocell CPLD for glue logic and I/O control, and a user-configurable DPLD for internal chip select decoding - both programmable via JTAG and supporting up to 100,000 Flash erase/write cycles and 1,000 PLD reconfigurations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Primary Flash | 4 Mbit (32K × 16), organized in 8 uniform sectors; enables bank-switched code execution and field firmware upgrades. |
| Secondary Flash | 256 Kbit with 4 sectors; used for boot code, configuration data, or parameter storage independent of main program space. |
| SRAM | 64 Kbit (32K × 16); provides fast, volatile working memory accessible at same bus timing as Flash. |
| PLD Capacity | Over 3000 equivalent gates; includes 16 OMCs and 24 IMCs for custom logic, address decoding, and peripheral interfacing. |
| Memory Access Time | 70 ns for both Flash and SRAM; ensures compatibility with 14 MHz 16-bit MCUs like 80C196 and MC68HC16. |
| Supply Voltage | 5 V ±10%; single-rail operation simplifies power design for legacy industrial and automotive control systems. |
| Data Retention | 15 years; guarantees long-term reliability of stored firmware and configuration without refresh. |
Pinout & Package
LQFP80 (80-lead, thin quad flat package), ECOPACK® compliant, with 52 dedicated I/O pins distributed across 7 ports (A–G), plus JTAG signals on Port E, power/ground, reset, and bus interface signals (ALE, RD, WR, CS, etc.).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PA0–PA7, PB0–PB7, PC0–PC7, PD0–PD7, PE0–PE7, PF0–PF7, PG0–PG7 | Configurable I/O port pins | 52 individually programmable pins supporting MCU I/O, PLD I/O, latched address output, or special functions (e.g., JTAG TCK/TMS/TDI/TDO on Port E). |
| CS0–CS3 | Chip select outputs | DPLD-generated active-low selects for external peripherals; decoded from address bus and control signals per user-defined logic. |
| ALE, RD, WR, OE, WE | MCU bus control inputs | Direct interface to 8/16-bit multiplexed or non-multiplexed buses; enables automatic timing alignment with host MCU cycles. |
| VCC, VSS | Power supply terminals | Single 5 V supply with dedicated power/ground pairs per quadrant to minimize noise coupling in mixed-signal operation. |
Key Features
| Feature | Design Value |
|---|---|
| Concurrent Flash operation | Read from one bank while erasing/writing the other - enables zero-downtime firmware updates in safety-critical systems. |
| Page register | 8-bit internal register expanding MCU address space by factor of 256 - eliminates need for external address latches in memory-constrained designs. |
| JTAG ISP | Built-in IEEE 1149.1-compliant port enabling full-chip programming, debugging, and boundary-scan testing without socketing or special hardware. |
| PLD-based decoding | User-configurable DPLD generates chip selects from address/control lines - replaces discrete logic and reduces BOM count in MCU peripheral interfaces. |
| Programmable power management | Automatic Power-down (APD) unit and configurable sleep modes reduce active current to <100 µA - extends battery life in portable instrumentation. |
Applications
| Industrial PLC Controller | Automotive Engine Control Unit (ECU) |
|---|---|
Use Scenario: Compact, field-upgradable controller managing I/O, PWM, and CAN communication in harsh environments. IC Role / Device Role / Timing Role: System-on-package replacing discrete Flash, SRAM, CPLD, and address decoders - handles MCU memory mapping, peripheral selection, and real-time firmware patching. Use Value: Dual-bank Flash allows safe over-the-air (OTA) updates without interrupting engine monitoring loops; JTAG enables factory programming and service diagnostics. |
Use Scenario: Embedded control module requiring deterministic response, EEPROM-like nonvolatile storage, and robust power cycling behavior. IC Role / Device Role / Timing Role: Memory and logic hub interfacing 80C196 or C16x MCU to sensors, actuators, and flash storage - manages boot sequence, memory protection, and watchdog-triggered recovery. Use Value: 15-year data retention and 100,000 Flash endurance ensure reliable calibration storage across vehicle lifetime; PLD logic enforces secure boot partitioning. |
| Medical Diagnostic Instrument | Legacy Industrial HMI Panel |
Use Scenario: Portable ultrasound or patient monitor with firmware update capability and low-power standby mode. IC Role / Device Role / Timing Role: Integrated memory and logic subsystem supporting 16-bit MCU - provides fast SRAM buffer, protected boot Flash, and configurable I/O for display and keypad interfaces. Use Value: Page register expands limited MCU address space to support larger GUI assets; APD mode reduces idle power to meet IEC 60601 leakage requirements. |
Use Scenario: Retrofit panel using aging 80C51XA or H8/300 MCU needing modern, socket-compatible memory/logic integration. IC Role / Device Role / Timing Role: Drop-in replacement for discrete EPROM + GAL + RAM combinations - replicates legacy memory map while adding ISP and enhanced reliability. Use Value: LQFP80 footprint and 5 V compatibility enable direct PCB replacement; JTAG eliminates costly UV erasers and programming fixtures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable system device applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD4235G2-90T | Same die, but in TQFP80 package with different thermal pad and moisture sensitivity level (MSL 3 vs MSL 2a for U variant). | Preferred for reflow-only assembly; requires updated stencil and oven profile versus LQFP80 (U). | Select when board-level reflow process mandates MSL 3 compliance or thermal pad grounding is required. |
| PSD4255G2-90U | Higher-density variant: 8 Mbit primary Flash + 512 Kbit secondary Flash; otherwise identical architecture, pinout, and timing. | Suitable for applications requiring larger firmware images or multi-application partitioning (e.g., dual-boot configurations). | Choose when >4 Mbit code space is needed - no redesign required beyond Flash image sizing and sector protection setup. |
Compared with PSD4235G2-90U, the -90T offers identical functionality in a thermally enhanced package for automated assembly, while the PSD4255G2-90U scales Flash capacity without altering logic resources or interface behavior - enabling seamless migration paths within the same PCB layout.
Availability
PSD4235G2-90U is available at Aetrix Electronics and suitable for industrial PLC controllers, automotive ECUs, medical diagnostic instruments, and legacy HMI panels requiring stable component supply, long-life support, and field-programmable flexibility.
Supply support for PSD4235G2-90U includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management devices, and programmable logic solutions for industrial, automotive, and consumer markets.
The PSD (Programmable System Device) product line was developed to integrate Flash memory, SRAM, and PLD logic into a single chip for 16-bit MCU-based systems - reducing board area, improving reliability, and enabling in-field firmware updates without hardware changes.
FAQ
Does PSD4235G2-90U support in-application programming (IAP)?
Yes. The device supports true in-application programming: the MCU can execute code from one Flash bank while simultaneously erasing or programming the other. This is enabled by hardware-level bank isolation and status flag monitoring (DQ6 toggle, DQ7 polling), allowing safe firmware updates without halting real-time tasks.
What MCU families are directly supported by the PSD4235G2-90U bus interface?
The PSD4235G2-90U natively supports 80C196, 80C186, 80C51XA, MC683xx, MC68HC16, H8/300, MMC2001, and C16x families. Its flexible bus timing generator and configurable control signal polarity (e.g., active-high/low CS, RD/WR) eliminate external glue logic for these architectures.
How is PLD configuration stored and retained?
PLD configuration is stored in the Secondary Flash memory and loaded automatically at power-on reset. The DPLD and CPLD logic definitions are programmed via JTAG into Flash sectors reserved for PLD bitstream storage, ensuring nonvolatile retention for 15 years and 1,000 reconfiguration cycles.
Is the page register accessible via standard MCU memory-mapped I/O?
Yes. The 8-bit page register resides at fixed I/O address 0x0000 (Port G Data-Out register) and is written using standard OUT instructions. Once set, it modifies the upper 8 bits of the 24-bit effective address generated by the PSD, enabling seamless expansion of the 16-bit MCU's address space to 16 MB.
PSD4235G2-90U Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 80-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 16-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 80-LQFP (12x12)
- Grade:
- -
- Qualification:
- -
PSD4235G2-90U FAQ
1.How can I place an order for PSD4235G2-90U through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD4235G2-90U on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD4235G2-90U reliable?
The price and inventory of PSD4235G2-90U are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD4235G2-90U is usually 5 days.
3.What payment methods are accepted for PSD4235G2-90U?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD4235G2-90U transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD4235G2-90U?
PSD4235G2-90U orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD4235G2-90U order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD4235G2-90U?
For technical support, including PSD4235G2-90U datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD4235G2-90U requirements.
6.How does Aetrix verify that PSD4235G2-90U is sourced from the original manufacturer or authorized distributors?
All PSD4235G2-90U products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD4235G2-90U meets industry standards.
7.What is the process for return or replacement of PSD4235G2-90U?
All PSD4235G2-90U units undergo pre-shipment inspection (PSI). If there is an issue with PSD4235G2-90U, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD4235G2-90U part is unused and in its original packaging.
Return procedure for PSD4235G2-90U:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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