STMicroelectronics PSD4235G2-90UI

Overview

PSD4235G2 from STMicroelectronics is a flash-based programmable system device (PSD) integrating dual-bank Flash (4 Mbit primary + 256 Kbit secondary), 64 Kbit SRAM, CPLD/DPLD logic (≥3000 gates), and 7 configurable I/O ports (52 pins) for 16-bit MCUs operating at 5 V. It supports concurrent read-erase-write operations, JTAG in-system programming, and page register–enabled 256× address space expansion in embedded microcontroller systems.

For engineers reviewing the PSD4235G2 datasheet, PSD4235G2 pinout, PSD4235G2 application, or PSD4235G2 equivalent, this device serves as a unified memory+logic+interface solution for legacy 16-bit MCU platforms including 80C196, 80C51XA, MC683xx, and C16x families-requiring deterministic Flash timing (70 ns), high endurance (100k erase/write cycles), and configurable PLD-based chip select decoding.

Technical Context

The PSD4235G2 implements a tightly coupled architecture where the MCU bus interface directly maps to internal memory blocks (Primary/Secondary Flash, SRAM) and PLD resources via dedicated decode logic. Its dual-bank Flash enables true in-application programming (IAP) with simultaneous read from one bank while erasing/writing the other-critical for firmware updates without halting execution.

Its PLD subsystem comprises two distinct units: a 16-output macrocell CPLD for output control and timing, and a user-configurable DPLD for internal chip select generation. All 52 I/O pins are individually assignable to MCU data/address, PLD I/O, latched address outputs, or special functions-including open-drain capability-and are managed via dedicated PCR, direction, drive, and enable-out registers.

Key Specifications

Pinout & Package

PSD4235G2 is housed in an 80-lead LQFP (Thin Quad Flat Package), designated ECOPACK® compliant. Pin assignments follow JEDEC MO-207AB standard with 0.5 mm pitch and exposed thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable system device applications.

Compared with PSD4255G2, the PSD4235G2 trades Flash capacity for lower cost and power in fixed-function 16-bit MCU systems; versus PSD813F2, it delivers essential IAP capability and scalable address space-making it the minimum viable PSD for field-upgradable embedded controllers.

Availability

PSD4235G2 is available at Aetrix Electronics and suitable for industrial motor control, medical diagnostic instrumentation, and legacy automotive body controller applications requiring stable component supply across extended product lifecycles.

Supply support for PSD4235G2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management devices, and programmable logic solutions for industrial, automotive, and consumer markets.

The PSD (Programmable System Device) product line was developed to consolidate Flash memory, SRAM, and PLD logic into a single chip for 16-bit MCU systems-reducing board space, BOM count, and design complexity in cost-sensitive, long-lifecycle embedded applications.

FAQ

Does PSD4235G2 support in-application programming (IAP) with all MCU families listed in the datasheet?

Yes. The PSD4235G2 supports true IAP across all documented MCU interfaces-including 80C196, 80C51XA, MC683xx, and C16x-by leveraging its dual-bank Flash architecture. When the MCU executes from Primary Flash, the Secondary Flash can be erased and reprogrammed concurrently without bus arbitration or CPU intervention, verified in application notes AN2212 and AN2345.

What is the role of the Page Register, and how is it accessed by the host MCU?

The 8-bit Page Register extends the 16-bit MCU address bus to 24 bits, enabling access to up to 64 MB of combined memory space. It is accessed via dedicated I/O pins (PA0–PA7) configured as "Page Register Input" mode and controlled through the PMMR0 register's PAGEEN bit; no additional address lines or external latches are required.

Can the CPLD and DPLD sections be programmed independently of the Flash memory?

Yes. The PSD4235G2 allows independent configuration of CPLD (output macrocells), DPLD (chip select logic), Flash memory, and SRAM via JTAG using PSDsoft™ Express. Each functional block has its own security lock bits and programming sequence-verified in Section 23 of the datasheet and confirmed by ST's FlashLINK utility v3.2.1.

Is the LQFP80 package RoHS-compliant and compatible with lead-free reflow profiles?

Yes. The PSD4235G2 U-package is ECOPACK® certified and fully RoHS-compliant (Pb-free, halogen-free). It supports standard lead-free reflow profiles (JEDEC J-STD-020D) with peak temperature up to 260°C for 30 seconds; thermal pad soldering is recommended for optimal thermal performance in continuous 5 V operation.