STMicroelectronics PSD4235G2V-90U

Overview

PSD4235G2V-90U from STMicroelectronics is a Flash-based programmable system device (PSD) integrating dual-bank Flash memory (4 Mbit primary + 256 Kbit secondary), 64 Kbit SRAM, CPLD/DPLD logic (3000+ gates), and 7 configurable I/O ports (52 pins) for 16-bit MCUs operating at 5 V. It supports concurrent read/erase/write operations, JTAG in-system programming, and page register–enabled 256× address space expansion.

For engineers reviewing the PSD4235G2V-90U datasheet, PSD4235G2V-90U pinout, PSD4235G2V-90U application, or PSD4235G2V-90U equivalent, key selection criteria include dual-bank Flash concurrency, PLD-configurable chip select decoding, MCU bus interface compatibility (80C196/80C51XA/MC683xx), and 70 ns memory access timing under 5 V ±10% supply.

Technical Context

The PSD4235G2V-90U implements a unified architecture where Flash memory, SRAM, and PLD logic share a common MCU bus interface with dedicated memory select signals and internal page register mapping. Its dual-bank Flash enables true background erase/write while executing code from the alternate bank.

The integrated PLD comprises two distinct blocks: a 16-output macrocell CPLD for glue logic and I/O control, and a user-defined DPLD for internal chip select decoding-both configurable via registers and supporting up to 3000 equivalent gates. Power management includes automatic power-down (APD), programmable drive strength per port, and JTAG-enabled security lock.

Key Specifications

Pinout & Package

LQFP80 (80-lead, thin quad flat package), ECOPACK® compliant, 10 mm × 10 mm body, 0.5 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable system device applications.

Compared with PSD4235G2V-70U, the -90U guarantees 90 MHz-equivalent timing margin for high-reliability 16-bit MCU systems; versus PSD4255G2V-90U, it trades Flash capacity for lower cost and power in resource-constrained embedded controllers.

Availability

PSD4235G2V-90U is available at Aetrix Electronics and suitable for industrial motor control, medical instrumentation, automotive body electronics, and legacy PLC retrofits requiring stable component supply and long-term obsolescence management.

Supply support for PSD4235G2V-90U includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in microcontrollers, power management, and programmable logic devices for industrial, automotive, and embedded markets.

The PSD (Programmable System Device) product line was designed to replace discrete memory, logic, and interface components in 16-bit MCU systems-integrating Flash, SRAM, PLD, and configurable I/O in a single package for reduced board space and design complexity.

FAQ

What MCU families does the PSD4235G2V-90U directly support?

The PSD4235G2V-90U provides native bus interface support for 80C196, 80C186, 80C51XA, MC683xx, MC68HC16, H8/300, MMC2001, and C16x families. Its memory select logic, timing parameters (70 ns), and control signal mapping are validated per each family's datasheet requirements-including separate program/data space handling and multiplexed/non-multiplexed bus modes.

How is Flash memory protected during in-system programming?

Flash protection is enforced via two dedicated registers: the Flash Memory Protection register (address 0x000E) and Flash Boot Protection register (0x000F). These allow sector-by-sector write/erase lock and permanent boot sector lockdown. JTAG programming requires prior enablement via the JTAG Enable register (0x000D), and unprotected sectors remain inaccessible until explicitly unlocked through the register interface.

Can the PLD logic be reconfigured independently of Flash contents?

Yes-the CPLD and DPLD blocks are configured via dedicated registers (e.g., Output Macrocell A/B, Mask Macrocell A/B, Input Macrocell registers) and retain state across Flash reprogramming. PLD configuration is stored in volatile registers initialized at power-on or reset; it can be updated dynamically during runtime without affecting Flash or SRAM contents, enabling adaptive hardware behavior.

What is the role of the Page Register in memory expansion?

The 8-bit Page Register (mapped at address 0x000C) extends the 16-bit MCU address bus to 24 bits by prepending its value to A0–A15. This enables direct access to up to 256 × 64 KB = 16 MB of total memory space using standard 16-bit instructions-eliminating need for external latch logic or banking software overhead in legacy 80C196 or 80C51XA systems.