STMicroelectronics PSD813F1A-12JI

Overview

PSD813F1A-12JI from STMicroelectronics is a Flash-based, in-system programmable (ISP) peripheral IC for 8-bit microcontroller systems, integrating 1 Mbit primary Flash, 256 Kbit secondary EEPROM, 16 Kbit SRAM, and a 3,000-gate PLD with 27 reconfigurable I/Os. It operates at 5 V ±10%, supports concurrent read/erase/write across memory banks, and features JTAG-compliant ISP for full-chip programming without MCU involvement - used in legacy industrial control modules requiring field-upgradable firmware and hardware logic reconfiguration.

For engineers reviewing the PSD813F1A-12JI datasheet, PSD813F1A-12JI pinout, PSD813F1A-12JI application, or PSD813F1A-12JI equivalent, key selection considerations include dual-bank nonvolatile memory concurrency, JTAG-based in-circuit programming capability, PLD macrocell count and I/O configurability, and compatibility with 80C51/68HC11 bus interfaces.

Technical Context

The PSD813F1A implements a tightly coupled architecture where the MCU bus directly accesses internal registers, Flash, EEPROM, SRAM, and PLD configuration via dedicated decode logic. Its DPLD handles chip-select generation while the CPLD provides 16 output macrocells and 24 input macrocells for custom glue logic.

Memory operation is managed through a page register enabling 256× address space expansion, and power management includes automatic power-down mode with standby current as low as 50 µA. The JTAG port supports IEEE 1149.1-compliant boundary-scan and full-device ISP - including Flash, EEPROM, PLD, and security bits - independent of host MCU state.

Key Specifications

Pinout & Package

PSD813F1A-12JI is housed in a 52-pin Plastic Leaded Chip Carrier (PLCC52) package per ECOPACK® standard, with 27 configurable I/Os, dedicated JTAG signals (TCK/TMS/TDI/TDO/TRST), memory control lines (CE#, OE#, WE#), and bus interface pins (AD0–AD7, A8–A19, RD#, WR#, CSI).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable MCU peripheral applications.

Compared with PSD813F1A-12JI, the PSD813F2A-12JI offers double Flash capacity with identical timing and compatibility, while the PSD833F2A-12JI introduces faster access, larger EEPROM, and hardened JTAG security - making it unsuitable for drop-in replacement in legacy timing-critical systems.

Availability

PSD813F1A-12JI is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy automotive ECUs, medical infusion pump controllers, and point-of-sale terminal baseboards requiring stable component supply and long-term obsolescence management.

Supply support for PSD813F1A-12JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in microcontrollers, power management, and programmable logic devices for industrial, automotive, and embedded markets.

The PSD (Programmable System Device) family was designed to replace discrete memory and glue logic in 8-bit MCU systems - delivering integrated Flash, EEPROM, SRAM, and PLD functionality in a single PLCC or PQFP package.

FAQ

Is PSD813F1A-12JI still in production despite the "Not for New Design" notice?

Yes - STMicroelectronics continues manufacturing PSD813F1A-12JI for existing product support, with documented last-time-buy dates and obsolescence notifications issued per industry standards. Aetrix Electronics maintains active inventory and offers lifecycle coordination services to ensure continuity for legacy systems.

Can PSD813F1A-12JI be programmed without a running MCU?

Yes - its IEEE 1149.1-compliant JTAG interface allows full-chip programming (Flash, EEPROM, PLD, configuration bits) while the device is blank or unpowered, requiring only a JTAG adapter and PSDsoft Express software - no host MCU firmware or boot sequence is needed.

What is the role of the Page Register in memory addressing?

The internal 8-bit Page Register extends the 20-bit address space to 28 bits, allowing up to 256 pages of 1 MB each. It is written via dedicated PSD registers and used automatically during memory access to select Flash/EEPROM/SRAM banks - eliminating external page-latch logic.

How does the PLD portion differ between DPLD and CPLD modes?

The DPLD implements fixed-function, high-speed chip-select decoding based on address and control signals; the CPLD provides user-programmable logic with 16 output macrocells (for custom I/O timing or bus arbitration) and 24 input macrocells (for status monitoring or interrupt aggregation), both configured via JTAG.