STMicroelectronics PSD813F1A-12UI

Overview

PSD813F1A-12UI from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontroller systems, integrating 1 Mbit primary Flash, 256 Kbit secondary EEPROM, 16 Kbit SRAM, and a 3,000-gate PLD with 27 reconfigurable I/Os. It operates at 5 V ±10%, supports concurrent read/erase/write across memory banks, and features JTAG-based ISP and a 256× address space expansion via internal page register - deployed in legacy industrial control and embedded instrumentation.

For engineers reviewing the PSD813F1A-12UI datasheet, PSD813F1A-12UI pinout, PSD813F1A-12UI application, or PSD813F1A-12UI equivalent, key selection considerations include dual-bank nonvolatile memory concurrency, JTAG-only ISP without MCU dependency, PLD macrocell configurability (16 OMCs / 24 IMCs), and 50 µA standby current in power-managed embedded systems.

Technical Context

The PSD813F1A implements a tightly coupled architecture where the MCU bus interface directly maps to internal registers, enabling zero-wait-state access to Flash, EEPROM, and SRAM. Its PLD subsystem comprises two independent blocks: a Decode PLD (DPLD) for user-defined chip-select logic and a Complex PLD (CPLD) with 16 output macrocells supporting combinatorial or registered outputs.

JTAG compliance (IEEE 1149.1) enables full-chip programming of Flash, EEPROM, PLD configuration bits, and security settings while soldered - no bootloader or host MCU required. The page register extends the 16-bit MCU address space to 24 bits by dynamically selecting memory banks, allowing seamless access to >64 KB of combined memory.

Key Specifications

Pinout & Package

PSD813F1A-12UI is housed in a 52-pin Plastic Quad Flat Package (PQFP) compliant with ECOPACK® environmental standards. Pin functions are validated per STMicroelectronics datasheet Rev 5 (October 2008), pages 10–13.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable memory and logic peripheral applications.

Compared with PSD813F1A-12UI, PSD813F2A-12UI offers double Flash capacity with zero architectural change, while PSD833F1A-12UI upgrades SRAM, thermal rating, and security - both retain identical PLD macrocell structure and JTAG ISP workflow.

Availability

PSD813F1A-12UI is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy MCU-based instrumentation, and automotive body control units requiring stable component supply and long-lifecycle support.

Supply support for PSD813F1A-12UI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, MEMS, and power management solutions for industrial, automotive, and consumer markets.

The PSD (Programmable System Device) family was engineered to replace discrete memory and logic in 8-bit MCU systems - integrating Flash, EEPROM, SRAM, and PLD into a single JTAG-programmable package for cost-sensitive, space-constrained embedded applications.

FAQ

Is PSD813F1A-12UI still in production despite the "Not for New Design" notice?

Yes - STMicroelectronics continues manufacturing PSD813F1A-12UI under active product status (as of datasheet Rev 5, October 2008). The "Not for New Design" designation reflects strategic roadmap focus on newer PSD generations, not obsolescence. Aetrix Electronics maintains verified inventory and long-term supply agreements for ongoing support of legacy systems.

Can the PLD logic be reconfigured independently of Flash/EPPROM programming?

Yes - the CPLD and DPLD configuration bits reside in dedicated nonvolatile cells and can be programmed, erased, or modified via JTAG without affecting Flash or EEPROM contents. PSDsoft Express allows separate compilation and download of PLD logic files (.jed) while preserving existing memory data.

What MCU families are natively supported by the PSD813F1A-12UI bus interface?

The device supports direct connection to 80C51, 80C251, 80C51XA, and 68HC11 MCUs without glue logic. Its flexible bus timing accommodates multiplexed (address/data shared) and non-multiplexed (separate address/data) configurations, with configurable wait states and byte-enable signals matching each architecture's protocol.

Does the 50 µA standby current include PLD and memory retention power?

Yes - the 50 µA specification (datasheet Section 6.4) represents total device current in Automatic Power-Down (APD) mode, with Flash, EEPROM, SRAM, and PLD configuration bits fully retained. This value is measured at VCC = 5 V, TA = 25°C, and all I/Os at high-impedance state, per AC/DC parameter table on page 77.