STMicroelectronics PSD813F1A-90J

Overview

PSD813F1A-90J from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating 1 Mbit primary Flash, 256 Kbit secondary EEPROM, 16 Kbit SRAM, and a 3,000-gate PLD with 27 reconfigurable I/Os. It operates at 5 V ±10%, supports concurrent read/erase/write across memory banks, and delivers 100,000 Flash erase/write cycles - used in legacy industrial control modules requiring field-upgradable firmware and configurable logic.

For engineers reviewing the PSD813F1A-90J datasheet, PSD813F1A-90J pinout, PSD813F1A-90J application, or PSD813F1A-90J equivalent, key selection criteria include dual-bank Flash concurrency, JTAG-based ISP without MCU involvement, PLD macrocell count (16 OMCs / 24 IMCs), page register–enabled 256× address expansion, and 50 µA standby current for low-power embedded systems.

Technical Context

The PSD813F1A implements a unified MCU-peripheral architecture with separate program/data space support, enabling direct bus interfacing to 80C51XA, 80C251, 80C31, and 68HC11 families. Its memory subsystem uses uniform sector organization: 8 sectors in primary Flash and 4 in EEPROM, each supporting individual protection and erase-suspend/resume functionality.

The integrated PLD comprises two distinct blocks: a Decode PLD (DPLD) for user-defined chip-select decoding and a Complex PLD (CPLD) with 16 output macrocells (OMCs) and 24 input macrocells (IMCs), both configurable via JTAG and supporting Turbo Bit acceleration for critical timing paths.

Key Specifications

Pinout & Package

PSD813F1A-90J is housed in a 52-pin PLCC (Plastic Leaded Chip Carrier) package, compliant with ECOPACK® environmental standards. Pin assignments are defined per the official STMicroelectronics datasheet Rev 5 (October 2008), with dedicated JTAG (TCK/TMS/TDI/TDO/TRST), memory control (OE#, WE#, CE#), PLD I/O (OMC/IMC signals), and MCU bus interface (AD0–AD7, A8–A15, RD#, WR#).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Flash+PLD peripheral applications.

Compared with PSD813F1A-90J, PSD813F2A-90J improves thermal robustness and Flash endurance for mission-critical use, while PSD833F2A-90J scales memory capacity without altering PLD logic or footprint - making both viable for lifecycle extension where the original part faces obsolescence pressure.

Availability

PSD813F1A-90J is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy medical device controllers, automotive diagnostic tools, and test equipment firmware adapters requiring stable component supply and long-term manufacturability.

Supply support for PSD813F1A-90J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, MEMS, and power management solutions since 1987.

The PSD (Programmable System Device) family was developed specifically to integrate Flash memory, EEPROM, SRAM, and configurable PLD logic into a single chip for 8-bit MCU-based embedded systems - reducing board space, BOM count, and firmware update complexity.

FAQ

Is PSD813F1A-90J still in production despite the "Not for New Design" notice?

Yes - STMicroelectronics continues manufacturing PSD813F1A-90J per its official product status documentation (Rev 5, October 2008). The "Not for New Design" designation reflects strategic roadmap focus on newer families, not discontinuation. Aetrix Electronics maintains active inventory and long-term supply agreements for this part in industrial and medical legacy programs.

Can PSD813F1A-90J be programmed without an MCU present on the board?

Yes - its IEEE 1149.1-compliant JTAG port supports full in-system programming of Flash, EEPROM, PLD logic, and configuration bits independently of any host MCU. This enables first-time programming of blank devices, factory pre-programming, and field firmware updates even if the MCU is unpowered or absent.

What is the role of the Page Register in memory expansion?

The 8-bit internal Page Register selects one of 256 memory pages, effectively multiplying the MCU's native address space (e.g., 64 KB) by 256 to access up to 16 MB. It is written via dedicated PSD control registers and used in conjunction with A0–A15 to generate full physical addresses - essential for large firmware images on 8-bit buses.

How does the PLD handle timing-critical address decoding?

The PSD813F1A's CPLD includes a Turbo Bit feature that bypasses standard macrocell propagation delay, delivering sub-10 ns decode paths for chip-select generation. Combined with dedicated DPLD for static decoding and configurable OMC/IMC registers, it ensures deterministic timing for high-speed 8-bit bus interfaces like 80C51XA and 68HC11.