STMicroelectronics PSD813F1A-90JI

Overview

PSD813F1A-90JI from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank nonvolatile memory (1 Mbit Flash + 256 Kbit EEPROM), 16 Kbit SRAM, a 3,000-gate PLD (DPLD/CPLD), 27 reconfigurable I/Os, and JTAG-based ISP. It operates at 5 V ±10%, supports concurrent read/erase/write, and delivers 100,000 Flash write cycles - used in legacy industrial MCU systems requiring field-upgradable firmware and configurable logic.

For engineers reviewing the PSD813F1A-90JI datasheet, PSD813F1A-90JI pinout, PSD813F1A-90JI application, or PSD813F1A-90JI equivalent, key selection criteria include concurrent Flash/EEPROM operation, JTAG-only ISP without MCU dependency, page register–enabled 256× address expansion, PLD macrocell count (16 OMCs/24 IMCs), and ECOPACK® PLCC52 packaging with 50 µA standby current.

Technical Context

The PSD813F1A implements a tightly coupled architecture where the MCU bus directly accesses internal registers via dedicated decode logic. Its DPLD handles chip-select generation while the CPLD provides 16 output macrocells and 24 input macrocells for custom glue logic, both supporting up to 1,000 erase/write cycles.

Memory subsystems operate independently: primary Flash (8 uniform sectors) and secondary EEPROM (4 uniform sectors) enable simultaneous access - e.g., executing code from Flash while updating configuration data in EEPROM. The internal page register extends the 8-bit MCU's address space to 24 bits, enabling seamless bank switching without external logic.

Key Specifications

Pinout & Package

PSD813F1A-90JI is housed in a 52-pin PLCC (Plastic Leaded Chip Carrier) package, ECOPACK® compliant, with gull-wing leads and body size 19.1 mm × 19.1 mm. Pinout validated per STMicroelectronics datasheet Rev 5 (pages 10–13).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Flash-configurable peripheral applications.

Compared with PSD813F2A-90JI, the PSD813F1A-90JI trades Flash capacity for lower cost and footprint in resource-constrained legacy systems; versus PSD833F2A-90JI, it maintains full 5 V compatibility and pin-for-pin fit but lacks 3.3 V efficiency and gate count scalability.

Availability

PSD813F1A-90JI is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy medical device controllers, and automotive body control units requiring stable component supply and long-lifecycle support.

Supply support for PSD813F1A-90JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and memory solutions for industrial, automotive, and consumer markets.

The PSD (Programmable System Device) family was developed to integrate Flash memory, EEPROM, SRAM, and PLD logic into a single chip for 8-bit MCU systems - reducing board space, BOM count, and design complexity in cost-sensitive embedded applications.

FAQ

Is PSD813F1A-90JI still in production despite the "Not for New Design" notice?

Yes - STMicroelectronics continues manufacturing PSD813F1A-90JI per its official product status documentation (October 2008 Rev 5). The "Not for New Design" designation reflects strategic roadmap guidance, not end-of-life; Aetrix Electronics maintains active inventory and long-term supply commitments for legacy system sustainment.

Can the JTAG port program the PLD independently of Flash and EEPROM?

Yes - the IEEE 1149.1 JTAG interface supports independent programming of the PLD configuration bits, Flash memory, EEPROM, and security registers. Each block has dedicated JTAG instructions (e.g., EXTEST for PLD, PROGRAM for Flash), allowing selective updates without affecting other memory regions.

What is the maximum operating frequency supported by the PSD813F1A-90JI bus interface?

The "-90" suffix denotes a 90 ns access time specification. When interfaced with an 80C51 or 68HC11 MCU, it supports up to 12 MHz system clock (83 ns cycle time), verified in ST's MCU interface examples (pages 47–51 of datasheet Rev 5); timing margins remain valid under worst-case 5 V ±10% and 85°C conditions.

Does the internal page register require MCU firmware intervention to function?

No - the page register is accessed via dedicated PSD control registers (e.g., PAGELATCH at offset 0x0000), mapped into the MCU's memory space. Once configured, it automatically remaps address lines A0–A7 to select one of 256 pages; no continuous firmware overhead is required for bank switching during normal execution.