STMicroelectronics PSD813F1A-90UI

Overview

PSD813F1A-90UI from STMicroelectronics is a Flash-based, in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating 1 Mbit primary Flash, 256 Kbit secondary EEPROM, 16 Kbit SRAM, and a 3,000-gate PLD with 16 output macrocells and 24 input macrocells. It supports concurrent memory operations, JTAG-based ISP, and page-register–enabled address expansion-used in legacy industrial control modules requiring field-upgradable firmware and configurable logic.

For engineers reviewing the PSD813F1A-90UI datasheet, PSD813F1A-90UI pinout, PSD813F1A-90UI application, or PSD813F1A-90UI equivalent, key selection criteria include dual-bank Flash/EPPROM endurance (100k/10k cycles), 27 reconfigurable I/Os with open-drain capability, 5 V±10% single-supply operation, JTAG-compliant in-system programming, and ECOPACK® PQFP52 package compatibility with 80C51/68HC11 buses.

Technical Context

The PSD813F1A implements a tightly coupled architecture where MCU bus signals directly access internal Flash, EEPROM, SRAM, and PLD resources via dedicated decode logic. Its DPLD handles chip-select generation while the CPLD provides 16 OMCs for custom I/O logic, supporting both latched address output and peripheral I/O modes.

JTAG interface enables full-chip ISP without MCU involvement-programming Flash, EEPROM, PLD configuration, and security bits independently. The internal page register extends the 8-bit MCU's address space by 256×, enabling seamless access to >64 KB of combined memory resources across separate program/data spaces.

Key Specifications

Pinout & Package

PSD813F1A-90UI is housed in an ECOPACK®-compliant 52-pin Plastic Quad Flat Package (PQFP52), with 27 reconfigurable I/Os distributed across Ports A–D, plus dedicated JTAG (TCK/TMS/TDI/TDO/TRST), reset (RESET), chip select (CSI), and power (VCC/GND) terminals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable peripheral applications.

Compared with PSD813F1A-90UI, PSD813F2A-90UI offers doubled Flash capacity with zero design impact, while PSD833F2A-90UI delivers higher reliability and security at the cost of full redesign-making the original optimal for cost-sensitive, volume-manufactured legacy systems.

Availability

PSD813F1A-90UI is available at Aetrix Electronics and suitable for industrial control modules, legacy medical equipment, automotive body electronics, and point-of-sale terminals requiring stable component supply and long-lifecycle support.

Supply support for PSD813F1A-90UI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for automotive, industrial, and consumer markets.

The PSD (Programmable System Device) family was developed to integrate Flash memory, EEPROM, SRAM, and programmable logic into a single chip for 8-bit MCU systems-reducing board space, BOM count, and design complexity in resource-constrained embedded applications.

FAQ

Is PSD813F1A-90UI still in production despite the "Not for New Design" notice?

Yes. STMicroelectronics continues manufacturing PSD813F1A-90UI under active product status per official documentation (Rev 5, October 2008). It remains available for legacy system repair, maintenance, and continuity builds-but ST does not recommend it for newly initiated designs due to newer alternatives like PSD833F2A.

Can the JTAG interface program Flash and PLD independently without MCU firmware involvement?

Yes. The IEEE 1149.1-compliant JTAG port provides full-chip ISP capability: Flash memory, EEPROM, PLD configuration bits, and security registers can all be programmed, verified, or erased while the device is soldered and completely blank-no MCU boot code or host processor is required.

What is the functional difference between the DPLD and CPLD sections in PSD813F1A-90UI?

The DPLD (Decode PLD) implements fixed-function internal chip-select decoding logic for memory and peripheral mapping. The CPLD (Complex PLD) contains 16 output macrocells and 24 input macrocells for user-defined combinational or sequential logic-such as bus arbitration, protocol translation, or custom interrupt generation.

Does PSD813F1A-90UI support in-application programming (IAP) of Flash memory?

Yes. The device supports IAP through MCU-initiated commands using standard Flash command sequences (e.g., unlock, program, erase). Data polling (DQ7) and toggle (DQ6) flags provide real-time status feedback, enabling safe runtime firmware updates without halting system operation.