STMicroelectronics PSD813F1VA-15M

Overview

PSD813F1VA-15M from STMicroelectronics is a programmable system device (PSD) integrating 128 KB Flash memory, 8 KB EEPROM, and 8 KB SRAM with dual-bank architecture, configurable PLD logic, and four I/O ports (A–D) supporting multiplexed/non-multiplexed address/data bus interfacing for 8-bit microcontrollers. It serves as a single-chip replacement for discrete glue logic, EPROM, EEPROM, and SRAM in legacy 8051 and Z80-based embedded control systems.

For engineers reviewing the PSD813F1VA-15M datasheet, PSD813F1VA-15M pinout, PSD813F1VA-15M application, or PSD813F1VA-15M equivalent, key selection criteria include Flash/EEPROM/SRAM partitioning, JTAG-based in-system programming (ISP), PLD macrocell count (128), I/O port configuration flexibility, and support for non-multiplexed 8-bit data bus operation with active-low RD/WR strobes.

Technical Context

The PSD813F1VA-15M implements a dual-memory architecture where Flash (128 KB) and EEPROM (8 KB) are independently erasable and programmable, enabling simultaneous code execution from Flash while updating EEPROM data during field firmware updates. Its PLD block contains 128 macrocells organized into two function blocks, supporting combinational and registered logic with user-defined output polarities and clock enables.

I/O ports A–D are individually configurable via internal registers: Port A supports address/data multiplexing; Ports B/C/D operate as standard bidirectional I/O or latch-controlled address/data lines. The integrated JTAG interface (IEEE 1149.1) enables full boundary-scan testing and direct Flash/EEPROM/PLD configuration without MCU intervention.

Key Specifications

Pinout & Package

PSD813F1VA-15M is housed in a 44-pin plastic quad flat package (PQFP) with 0.8 mm lead pitch, designed for surface-mount assembly and thermal reliability in industrial temperature range (–40°C to +85°C).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable memory + logic applications.

Compared with PSD813F1VA-15M, the PSD813F2VA-15M offers double Flash capacity with zero design impact, while the ATF16V8C-15PU forces external memory dependency and loses JTAG-based field update capability-making it unsuitable for firmware-hub applications.

Availability

PSD813F1VA-15M is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy medical device controllers, and automotive body control units requiring stable component supply and long-term lifecycle assurance.

Supply support for PSD813F1VA-15M includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in microcontrollers, power management, and programmable logic devices for industrial, automotive, and consumer markets.

The PSD family was developed to replace discrete memory and glue logic in 8-bit embedded systems, targeting cost-sensitive, space-constrained applications needing field-programmable nonvolatile storage and configurable logic in one package.

FAQ

Does PSD813F1VA-15M support in-system programming without removing it from the PCB?

Yes. The device features full IEEE 1149.1 JTAG compliance, enabling complete Flash, EEPROM, PLD, and configuration register programming while soldered to the target board. No external programmer socket or MCU involvement is required-only TCK, TMS, TDI, and TDO connections to a JTAG host are needed.

Can the 8 KB EEPROM be used for storing calibration data that must survive 100+ years?

Yes. STMicroelectronics specifies EEPROM data retention of ≥100 years at 25°C and ≥40 years at 85°C. Each byte supports ≥100,000 erase/write cycles. The EEPROM is organized in uniform 64-byte sectors, allowing byte-level writes without sector erasure overhead.

How does the PLD block integrate with the microcontroller's address and data bus?

The PLD accepts A0–A15 and D0–D7 as primary inputs, plus RD, WR, and CS signals. It generates custom outputs like chip selects, wait states, or peripheral enables-mapped directly to Port C or D pins. Logic equations are defined via ST's PSDSoft tool and programmed into the device's configuration memory.

Is there hardware write protection for Flash and EEPROM sections?

Yes. Dedicated lock bits in the Configuration Register prevent accidental writes or erases. Flash sectors can be individually protected; EEPROM supports byte-level write protection via software-controlled lock bits. Protection status is retained through power cycles and verified during JTAG readback.