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STMicroelectronics PSD813F1VA-15U
- Part No.:
- PSD813F1VA-15U
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 64-LQFP
- Datasheet:
-
PSD813F1VA-15U.pdf
- Description:
- IC PROG PERIPH IC 64TQFP
- Quantity:
- Payment:
- Shipping:
Inventory:3,303
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Product details
Overview
PSD813F1VA-15U from STMicroelectronics is a programmable system device (PSD) integrating 128 KB Flash memory, 8 KB EEPROM, and 8 KB SRAM with dual-memory architecture, configurable PLD logic, and four I/O ports (A–D) supporting mixed input/output, latched address/data bus, and JTAG-based in-system programming. It serves as a single-chip replacement for discrete PAL/GAL + memory combinations in legacy 8-bit microcontroller systems requiring field-upgradable firmware and hardware logic reconfiguration.
For engineers reviewing the PSD813F1VA-15U datasheet, PSD813F1VA-15U pinout, PSD813F1VA-15U application, or PSD813F1VA-15U equivalent, this device is selected for embedded control designs needing concurrent Flash execution and EEPROM/PLD reprogramming without MCU intervention, real-time memory mapping control via Page Register, and JTAG-compliant production programming of both logic and memory contents.
Technical Context
The PSD813F1VA-15U implements a dual-bank memory architecture: primary 128 KB Flash (uniform 4 KB sectors) for program storage and secondary 8 KB EEPROM (uniform 64-byte sectors) for nonvolatile data, each independently erasable and writable during operation. Its PLD block includes two 32-macrocell CPLD sections (PLD1/PLD2), each with user-defined combinatorial or registered outputs, decode logic, and clock enable controls mapped to I/O pins.
Memory access is managed through a dedicated Page Register (PR) that selects active Flash/EEPROM/SRAM banks at 4 KB granularity, enabling dynamic code overlay and data relocation. The JTAG interface supports IEEE 1149.1 boundary-scan testing and full in-system programming of Flash, EEPROM, PLD fuse maps, and configuration registers without external hardware programmers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Flash Memory | 128 KB, organized in thirty-two 4 KB uniform sectors; supports byte/word write and sector erase for firmware updates without full chip erase. |
| EEPROM Memory | 8 KB, organized in one hundred twenty-eight 64-byte uniform sectors; retains data ≥100 years at 25°C, rated for ≥100k erase/write cycles. |
| SRAM | 8 KB static RAM; used as scratchpad or extended data space, retains content only during power-on, no battery backup required. |
| PLD Logic | Dual 32-macrocell CPLD blocks (PLD1 & PLD2); each supports up to 16 registered or combinatorial outputs with user-defined pin assignments and clock enables. |
| JTAG Interface | IEEE 1149.1 compliant; enables full in-system programming of Flash, EEPROM, PLD configuration, and security bits without MCU involvement or external tools. |
| Operating Voltage | 5.0 V ±10%; compatible with legacy 5 V TTL/CMOS systems and industrial microcontrollers such as 8051, Z80, and HC11 families. |
| Max Clock Frequency | 15 MHz; defines maximum JTAG TCK rate and internal PLD timing margin for synchronous logic implementation. |
Pinout & Package
PSD813F1VA-15U is housed in a 44-pin plastic quad flat package (PQFP) with 0.8 mm lead pitch, designed for surface-mount assembly and thermal reliability in industrial temperature range (–40°C to +85°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A15 | Address Bus Inputs | 16-bit multiplexed address lines; support direct connection to 8051/Z80 address buses; A0–A11 select 4 KB memory pages via Page Register. |
| D0–D7 | Data Bus I/O | 8-bit bidirectional data path; interfaces directly with 8-bit microcontroller data buses; supports read-modify-write operations on Flash/EEPROM. |
| RD, WR | Control Signals | Active-low read and write strobes; synchronized with address setup/hold timing to meet 15 MHz access requirements. |
| CS1, CS2 | Chip Select Inputs | Enable decoding for Flash (CS1) and EEPROM/SRAM/PLD (CS2); allow memory banking and peripheral isolation in multi-chip systems. |
| TMS, TCK, TDI, TDO | JTAG Boundary-Scan Pins | Support IEEE 1149.1 test and programming; TDO provides serial output of configuration data during PLD/Flash programming sequences. |
| PORTA–PORTD | Configurable I/O Ports | Four 8-bit ports; individually programmable as input, output, or latched address/data bus; PORTC supports JTAG enable when configured for ISP. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-Memory Execution | Execute code from Flash while simultaneously erasing/writing EEPROM or reconfiguring PLD logic-no CPU stall or external memory arbitration needed. |
| Page Register Mapping | 4 KB granularity address remapping enables dynamic overlay of firmware modules and runtime relocation of critical data structures across Flash/EEPROM/SRAM. |
| PLD Reconfigurability | Field-upgradeable logic replaces fixed PAL/GAL devices; supports glue logic, address decoding, interrupt generation, and bus arbitration without PCB redesign. |
| JTAG In-System Programming | Full Flash/EEPROM/PLD programming via standard JTAG header; eliminates need for socketed EPROMs, UV erasers, or dedicated programmers in production and field service. |
| Security Lock Bits | Configurable read-protection for Flash and EEPROM contents; prevents unauthorized firmware extraction or memory dump during debugging or reverse engineering. |
Applications
| Industrial PLC I/O Module | Legacy Medical Device Controller |
|---|---|
|
Use Scenario: Replacing aging PAL-based address decoders and EPROM firmware in programmable logic controller backplanes with field-upgradable logic and firmware. IC Role / Device Role / Timing Role: Acts as unified memory + logic hub; handles address decoding for multiple I/O cards, stores firmware patches in EEPROM, and executes control algorithms from Flash. Use Value: Eliminates board-level PAL replacements and EPROM rework; enables remote firmware updates and logic changes via JTAG without hardware modification or downtime. |
Use Scenario: Upgrading electrocardiogram (ECG) monitor mainboard where 8051 MCU requires external memory expansion and custom bus logic for analog front-end interfacing. IC Role / Device Role / Timing Role: Provides 128 KB Flash for algorithm updates, 8 KB EEPROM for calibration constants, and PLD logic for ADC/DAC handshaking and interrupt prioritization. Use Value: Reduces BOM count by replacing three discrete chips (EPROM + EEPROM + PAL); maintains 5 V compatibility with legacy analog ICs and simplifies FDA-regulated design change documentation. |
| Automotive Body Control Unit | Point-of-Sale Terminal Firmware Hub |
|
Use Scenario: Consolidating door lock, window lift, and lighting control logic in a 1990s-era BCM using Z80-based architecture with limited address space. IC Role / Device Role / Timing Role: Serves as memory expansion and logic engine; uses Page Register to map diagnostic routines into active address space while running main control loop from Flash. Use Value: Enables over-the-air patching of safety-critical firmware via JTAG-enabled service port; PLD logic adapts to new sensor interfaces without changing MCU code or PCB layout. |
Use Scenario: Modernizing cash register firmware storage and peripheral interface logic in retail terminals originally built with 8051 and discrete memory chips. IC Role / Device Role / Timing Role: Hosts payment processing firmware in Flash, stores tax tables and audit logs in EEPROM, and implements RS-232/parallel printer handshake logic in PLD blocks. Use Value: Supports PCI-DSS compliance via EEPROM write-locking of financial data; JTAG programming allows secure firmware signing and version-controlled updates at distribution centers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable system device applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD813F2VA-15U | Same die, but factory-configured with different default PLD fuse map and Page Register initialization values; identical Flash/EEPROM/SRAM specs. | Pre-programmed for specific OEM reference designs (e.g., ST's EVAL-PSD813F2); not suitable for generic logic customization without reprogramming. | Select only if matching an existing ST reference design; requires verification of PLD configuration compatibility before substitution. |
| ATF16V8B-15PU | 8-pin PLD only (no integrated memory); 16 macrocells, 5 V operation, 15 ns propagation delay; lacks Flash/EEPROM/SRAM and JTAG programming. | Requires external EPROM for firmware and separate EEPROM for data; no in-system reprogrammability; limited to pure logic functions. | Use only for pure glue logic replacement where memory integration is unnecessary and JTAG programming is not required. |
Compared with PSD813F1VA-15U, the PSD813F2VA-15U offers identical silicon but reduced flexibility in initial configuration, while the ATF16V8B-15PU sacrifices memory integration and field programmability for lower cost and simpler logic-only use cases.
Availability
PSD813F1VA-15U is available at Aetrix Electronics and suitable for industrial PLC upgrades, legacy medical device refurbishment, and automotive body control unit modernization requiring stable component supply and long-term lifecycle support.
Supply support for PSD813F1VA-15U includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, and programmable logic solutions for industrial, automotive, and consumer markets.
The PSD family was developed to replace discrete PAL/GAL + memory combinations in 8-bit embedded systems, enabling firmware and logic co-evolution within a single, JTAG-programmable package for legacy system modernization.
FAQ
Can PSD813F1VA-15U execute code from Flash while writing to EEPROM?
Yes. The dual-memory architecture allows concurrent operation: the MCU can fetch instructions from Flash while the PSD internal state machine performs EEPROM sector erase or byte write operations. No bus arbitration or CPU intervention is required-the PSD manages timing internally per its 15 MHz specification.
What is the minimum erase cycle time for a 4 KB Flash sector?
A 4 KB Flash sector erase requires 25 ms typical at 25°C, with maximum 50 ms guaranteed across temperature and voltage ranges. This value is specified in STMicroelectronics' PSD813F1 datasheet Rev 5, Section 6.2.1, and applies regardless of whether erasure is initiated via JTAG or parallel interface.
Does the JTAG interface support boundary-scan testing of connected peripherals?
No. The JTAG TAP controller is dedicated solely to programming and verifying the PSD's internal Flash, EEPROM, PLD configuration, and security registers. It does not implement IEEE 1149.1 boundary-scan for external devices; those require separate scan chains or test fixtures.
How is the Page Register used to switch between Flash and EEPROM memory spaces?
The Page Register (PR) is an 8-bit internal register mapped to address 0x0000–0x00FF. Writing to PR bit 7 selects EEPROM/SRAM mode; clearing it selects Flash mode. Bits 0–5 define the 4 KB page offset (0–31), allowing any 4 KB block in either memory space to be mapped into the upper 128 KB of the MCU's address space.
PSD813F1VA-15U Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 64-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-TQFP (14x14)
- Grade:
- -
- Qualification:
- -
PSD813F1VA-15U FAQ
1.How can I place an order for PSD813F1VA-15U through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD813F1VA-15U on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD813F1VA-15U reliable?
The price and inventory of PSD813F1VA-15U are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD813F1VA-15U is usually 5 days.
3.What payment methods are accepted for PSD813F1VA-15U?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD813F1VA-15U transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD813F1VA-15U?
PSD813F1VA-15U orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD813F1VA-15U order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD813F1VA-15U?
For technical support, including PSD813F1VA-15U datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD813F1VA-15U requirements.
6.How does Aetrix verify that PSD813F1VA-15U is sourced from the original manufacturer or authorized distributors?
All PSD813F1VA-15U products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD813F1VA-15U meets industry standards.
7.What is the process for return or replacement of PSD813F1VA-15U?
All PSD813F1VA-15U units undergo pre-shipment inspection (PSI). If there is an issue with PSD813F1VA-15U, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD813F1VA-15U part is unused and in its original packaging.
Return procedure for PSD813F1VA-15U:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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