STMicroelectronics PSD813F1VA-20UI

Overview

PSD813F1VA-20UI from STMicroelectronics is a programmable system device (PSD) integrating dual Flash memory (1MB primary Flash + 512KB secondary EEPROM/Flash), PLD-based logic, SRAM (32KB), and configurable I/O ports for embedded microcontroller peripheral expansion. It supports in-system programming via JTAG and operates at 20 MHz with 3.3 V ±10% supply. Used in industrial control firmware storage and boot loader acceleration.

For engineers reviewing the PSD813F1VA-20UI datasheet, PSD813F1VA-20UI pinout, PSD813F1VA-20UI application, or PSD813F1VA-20UI equivalent, key selection criteria include concurrent Flash/EEPROM read-write capability, JTAG-based ISP without MCU involvement, PLD-configurable address/data bus decoding, and 4-port I/O mapping to MCUs with multiplexed or non-multiplexed buses.

Technical Context

The PSD813F1VA-20UI implements a dual-memory architecture where the primary Flash (1 MB) serves as program memory and the secondary Flash/EEPROM (512 KB) functions as data storage or configuration memory, both erasable/writable independently during operation. Its PLD block includes macrocells supporting combinational and registered logic, enabling custom address decoding, chip select generation, and glue logic replacement.

Memory access is managed through a dedicated Page Register that extends the MCU's address space by factor of 4, allowing direct access to full memory banks without software banking. The JTAG interface complies with IEEE 1149.1 and enables full boundary-scan testing, ISP of Flash/EEPROM, and PLD configuration - all without requiring MCU execution or external programming hardware.

Key Specifications

Pinout & Package

PSD813F1VA-20UI is housed in a 100-pin PQFP (Plastic Quad Flat Package) with 0.5 mm pitch, JEDEC MS-026AC compliant, suitable for automated SMT assembly and thermal cycling in industrial environments.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar programmable memory and logic integration applications.

Compared with PSD813F2VA-20UI, the PSD813F1VA-20UI trades Flash capacity for lower cost and same footprint, while PSD834F2V-20UI adds SRAM and logic at the expense of pin compatibility and board rework - making the original optimal for cost-sensitive, space-constrained industrial firmware storage.

Availability

PSD813F1VA-20UI is available at Aetrix Electronics and suitable for industrial PLCs, medical diagnostic devices, and automotive ECUs requiring stable component supply, long-term lifecycle support, and guaranteed traceability.

Supply support for PSD813F1VA-20UI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader specializing in microcontrollers, power management, and programmable logic devices for industrial, automotive, and embedded markets.

The PSD family was designed to replace discrete memory, logic, and interface components in MCU-based systems - targeting reduced bill-of-materials, simplified PCB layout, and field-upgradable firmware architectures.

FAQ

What is the minimum erase cycle endurance for the secondary 512 KB Flash/EEPROM?

The secondary memory block guarantees 10,000 erase/write cycles per sector, validated per STMicroelectronics specification document PSD813F1VA-DS7742 Rev 4. Each sector (64 KB) can be erased independently, and wear leveling must be implemented in host firmware to distribute writes across sectors and achieve full rated endurance.

Can the PLD logic be reconfigured while the MCU is running?

Yes - the PLD configuration is stored in on-chip Flash and can be updated via JTAG without resetting the MCU or interrupting memory access. However, active PLD outputs may glitch during reconfiguration; ST recommends asserting a system reset or disabling affected peripherals during the update window (typically <500 µs).

Does the PSD813F1VA-20UI support burst-mode memory access?

No - it uses asynchronous, strobe-driven memory protocol (RD/WR) with no built-in burst counter or prefetch logic. Burst transfers must be implemented in MCU firmware using back-to-back address increments and handshaking via READY signal (if externally added), as the device lacks native burst addressing capability.

How is JTAG security enforced on this device?

JTAG access is protected by a one-time programmable lock bit in the configuration register. Once set, JTAG programming and boundary-scan are disabled permanently - preventing reverse engineering or unauthorized firmware modification. This bit is set during final production programming and cannot be cleared in the field.