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STMicroelectronics PSD813F2A-70J
- Part No.:
- PSD813F2A-70J
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 52-LCC (J-Lead)
- Datasheet:
-
PSD813F2A-70J.pdf
- Description:
- IC PROG PERIPH IC 52PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,492
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Product details
Overview
PSD813F2A-70J from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (1 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, and a 3000-gate PLD with CPLD/DPLD architecture. It supports concurrent read-erase-write operations and features an internal page register for 256× address space expansion, used in legacy 80C51/80C251/68HC11-based embedded control systems.
For engineers reviewing the PSD813F2A-70J datasheet, PSD813F2A-70J pinout, PSD813F2A-70J application, or PSD813F2A-70J equivalent, key selection criteria include ISP JTAG support, dual-bank Flash concurrency, PLD-based chip select decoding, and 5 V operation with ECOPACK® PLCC52 packaging.
Technical Context
This device functions as a memory and logic co-processor for 8-bit MCUs, interfacing via multiplexed or non-multiplexed 8-bit buses. Its dual-bank Flash enables background programming while executing code from the other bank, and its DPLD provides user-defined internal chip select decoding independent of MCU address lines.
The integrated PLD includes 16 output macrocells (OMCs) and 24 input macrocells (IMCs), supporting both combinatorial and synchronous/asynchronous clocked logic. The page register extends the MCU's external address space by dynamically mapping 256 pages of 64 KB each, enabling access to >16 MB total memory without bus width extension.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Primary Flash Memory | 1 Mbit (8 × 128 KB uniform sectors); enables firmware storage with sector-level erase granularity. |
| Secondary Flash Memory | 256 Kbit (4 × 64 KB uniform sectors); used for parameter storage or boot code with independent erase/write control. |
| SRAM Capacity | 256 Kbit (32 KB); provides fast, non-volatile-critical data buffer accessible at full bus speed. |
| I/O Ports | 27 reconfigurable pins; configurable as MCU I/Os, PLD I/Os, latched address outputs, or special function signals. |
| PLD Logic Density | ~3000 usable gates; implements custom address decoders, glue logic, or state machines without external components. |
| Page Register Function | 256-page address expansion; maps MCU's 16-bit address bus to 24-bit physical space for memory banking. |
| JTAG Interface | IEEE 1149.1-compliant serial port; enables full-chip in-system programming and boundary-scan testing. |
Pinout & Package
PSD813F2A-70J is housed in a 52-pin PLCC (Plastic Leaded Chip Carrier) package compliant with ECOPACK® environmental standards. Pin assignments follow STMicroelectronics' PLCC52 layout per Appendix B of Doc ID 7833 Rev 7.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, GND | Power supply terminals | 5 V ±10% core supply; separate analog/digital ground not required - single 5 V rail powers all logic and memory blocks. |
| A0–A15 | Address inputs | 16-bit multiplexed or non-multiplexed address bus interface compatible with 80C51, 80C251, and 68HC11 MCUs. |
| D0–D7 | Data bus I/O | 8-bit bidirectional data path; supports byte-wide read/write cycles synchronized to RD/WR control signals. |
| RD, WR, CS | Memory control signals | Standard read/write strobes and chip select; enable timing-compliant access to Flash, SRAM, and PLD registers. |
| TCK, TMS, TDI, TDO | JTAG test interface | IEEE 1149.1 boundary-scan pins on Port C; allow in-system programming and debug without removing the device. |
| PC0–PC7 | JTAG-capable I/O port | Port C pins double as JTAG signals when JTAGEN bit is set; retain I/O functionality in non-debug modes. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank Flash concurrency | Read from one bank while erasing/writing the other - eliminates MCU stall during firmware updates. |
| Configurable I/O port modes | 27 pins support six operating modes (MCU I/O, PLD I/O, latched address, etc.), reducing external logic count. |
| User-defined DPLD decoding | Internal chip select generation replaces discrete decoder ICs - simplifies PCB layout and improves timing margin. |
| Page register address expansion | Extends 16-bit MCU address space to 24 bits - enables large memory maps without hardware address multiplexing. |
| Programmable power management | Automatic Power-down (APD) unit reduces current to <100 µA during idle - extends battery life in portable 8-bit systems. |
Applications
| Industrial PLC I/O Expansion | Legacy Automotive ECU Retrofit |
|---|---|
Use Scenario: Adding non-volatile program storage and custom address decoding to aging 80C51-based PLC controllers. IC Role / Device Role / Timing Role: Acts as memory hub and glue logic replacement - manages Flash/SRAM access and generates peripheral chip selects. Use Value: Eliminates need for external EPROM, SRAM, and 74-series decoders, reducing BOM cost and board area by 35%. |
Use Scenario: Upgrading fuel injection control units using 68HC11 MCUs with extended memory and secure firmware update capability. IC Role / Device Role / Timing Role: Provides in-system programmable Flash for calibration tables and PLD-based sensor interface logic. Use Value: Enables field firmware updates via JTAG without disassembly; DPLD implements timing-critical camshaft position decoding. |
| Medical Instrument Bootloader | Point-of-Sale Terminal Memory Subsystem |
Use Scenario: Secure bootloader implementation in ISO 13485-certified patient monitor with dual-bank Flash fail-safe update. IC Role / Device Role / Timing Role: Hosts verified boot code in protected primary Flash sector and runtime parameters in secondary Flash. Use Value: Concurrent Flash operation ensures zero-downtime firmware validation and rollback - meeting IEC 62304 Class C requirements. |
Use Scenario: Memory expansion for 80C251-based thermal receipt printers requiring persistent configuration and font storage. IC Role / Device Role / Timing Role: Supplies 256 Kbit SRAM for print buffer and dual Flash banks for firmware + localized language fonts. Use Value: Page register enables seamless access to >64 KB font sets; open-drain I/Os drive LED status indicators directly. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Flash+PLD peripheral applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD833F2-90J | 2 Mbit primary Flash (vs. 1 Mbit), 90 ns access time (vs. 70 ns), same PLCC52 package and pinout. | Supports larger firmware images; requires tighter MCU wait-state timing due to slower access. | Select when firmware size exceeds 1 Mbit and system timing budget allows 90 ns cycle. |
| PSD813F4-70J | Same 1 Mbit primary Flash but 512 Kbit secondary Flash (vs. 256 Kbit); identical timing and I/O structure. | Better suited for applications needing larger non-volatile parameter storage without increasing primary code space. | Choose when calibration data or logging buffers require >256 Kbit dedicated Flash, with no change to existing layout. |
Compared with PSD813F2A-70J, PSD833F2-90J trades speed for capacity, while PSD813F4-70J increases secondary Flash density without altering performance or footprint - enabling targeted upgrades within legacy designs.
Availability
PSD813F2A-70J is available at Aetrix Electronics and suitable for industrial PLC retrofit, legacy automotive ECU modernization, and medical instrument bootloader development requiring stable component supply and long-lifecycle support.
Supply support for PSD813F2A-70J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and memory solutions for industrial, automotive, and consumer markets.
The PSD8XXFX product line was engineered specifically to replace discrete memory and logic components in 8-bit MCU systems, delivering integrated Flash, SRAM, PLD, and ISP capability in a single ECOPACK® package.
FAQ
Is PSD813F2A-70J pin-compatible with other PSD8XXFX variants in PLCC52?
Yes - all PSD8XXFX devices in PLCC52 (J-suffix) share identical pinouts and electrical characteristics per Doc ID 7833 Rev 7 Table 3 and Section 2. This includes consistent signal placement for A0–A15, D0–D7, RD/WR/CS, and JTAG pins, enabling drop-in replacement within the same memory/PLD capacity class.
What MCU families does PSD813F2A-70J natively support?
It supports 80C51, 80C251, 80C51XA, and 68HC11 families via documented bus interface modes in Sections 15.1–15.8. Each is validated with specific control signal mappings (e.g., RD/WR polarity, address latch enable timing) and includes example schematics for direct integration without level-shifting or timing adapters.
How is Flash sector protection implemented?
Sector protection is controlled via the Flash Protection register (Section 10.1), where individual bits lock/unlock each of the 12 uniform Flash sectors (8 primary + 4 secondary). Once locked, sectors resist erase/write commands until unlocked via a 6-byte security sequence issued through the JTAG port or MCU interface.
Does PSD813F2A-70J support 3 V operation?
No - PSD813F2A-70J is a 5 V-only device specified for VCC = 4.5 V to 5.5 V (Table 40). The 3 V variants (e.g., PSD813F2V-70J) use different part numbering and are not interchangeable due to distinct DC/AC characteristics, internal voltage regulation, and I/O threshold levels.
PSD813F2A-70J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 52-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 52-PLCC (19.1x19.1)
- Grade:
- -
- Qualification:
- -
PSD813F2A-70J FAQ
1.How can I place an order for PSD813F2A-70J through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD813F2A-70J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD813F2A-70J reliable?
The price and inventory of PSD813F2A-70J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD813F2A-70J is usually 5 days.
3.What payment methods are accepted for PSD813F2A-70J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD813F2A-70J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD813F2A-70J?
PSD813F2A-70J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD813F2A-70J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD813F2A-70J?
For technical support, including PSD813F2A-70J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD813F2A-70J requirements.
6.How does Aetrix verify that PSD813F2A-70J is sourced from the original manufacturer or authorized distributors?
All PSD813F2A-70J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD813F2A-70J meets industry standards.
7.What is the process for return or replacement of PSD813F2A-70J?
All PSD813F2A-70J units undergo pre-shipment inspection (PSI). If there is an issue with PSD813F2A-70J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD813F2A-70J part is unused and in its original packaging.
Return procedure for PSD813F2A-70J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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