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STMicroelectronics PSD813F2A-90J
- Part No.:
- PSD813F2A-90J
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 52-LCC (J-Lead)
- Datasheet:
-
PSD813F2A-90J.pdf
- Description:
- IC PROG PERIPH IC 52PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,593
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Product details
Overview
PSD813F2A-90J from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (1 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, and a CPLD/DPLD logic block with >3000 gates. It supports concurrent read/erase/write operations and features an internal page register enabling 256× address space expansion - deployed in legacy industrial control systems interfacing 80C51XA and 68HC11 MCUs.
For engineers reviewing the PSD813F2A-90J datasheet, PSD813F2A-90J pinout, PSD813F2A-90J application, or PSD813F2A-90J equivalent, key selection criteria include ISP JTAG support, dual-bank Flash concurrency, PLD-based chip select decoding, and 5 V operation with ECOPACK® PLCC52 packaging.
Technical Context
The PSD813F2A-90J implements a tightly coupled memory-peripheral architecture where the primary Flash (32K × 8, 8 uniform sectors) and secondary Flash (64K × 4, 4 uniform sectors) operate independently under JTAG-controlled ISP. Its PLD subsystem comprises 24 input macrocells (IMCs) and 16 output macrocells (OMCs), configurable as CPLD or DPLD for address decoding and glue logic replacement.
It interfaces via multiplexed or non-multiplexed 8-bit MCU buses (e.g., 80C31, 80C251, 68HC11), uses a dedicated JTAG port (TCK/TMS/TDI/TDO on Port C pins), and includes automatic power-down (APD) with programmable timeout - all managed through dedicated registers including PMMR0/PMMR2 and OMC mask registers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Primary Flash | 1 Mbit (32K × 8, 8 uniform sectors); enables firmware storage with sector-level erase granularity for field updates. |
| Secondary Flash | 256 Kbit (64K × 4, 4 uniform sectors); provides isolated boot code or configuration data storage independent of main Flash. |
| SRAM | 256 Kbit (32K × 8); serves as fast-access data buffer or stack memory for 8-bit MCUs without on-chip RAM. |
| PLD Logic Capacity | >3000 gates; replaces discrete glue logic with user-defined decode, timing, and control functions in embedded systems. |
| I/O Ports | 27 reconfigurable pins; supports MCU I/O, PLD I/O, latched address output, and open-drain mode (16 pins). |
| Page Register | 8-bit internal register; expands MCU address space by factor of 256, enabling access to >16 MB memory map using 16-bit address bus. |
| Operating Voltage | 5 V ±10%; compatible with legacy 5 V TTL/CMOS MCU families and eliminates level-shifting requirements. |
| Max Access Time | 90 ns; guarantees timing compliance with 80C51XA and 68HC11 at maximum clock frequencies without wait states. |
Pinout & Package
PSD813F2A-90J is housed in a 52-pin PLCC (Plastic Leaded Chip Carrier) package compliant with ECOPACK® environmental standards. Pin assignments follow STMicroelectronics' PLCC52 layout per Appendix B of Doc ID 7833 Rev 7.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, GND | Power supply and ground | 5 V core and I/O supply; decoupling required within 1 cm of pins for stable operation at 90 ns access. |
| A0–A15 | Address inputs | 16-bit address bus interface; supports both multiplexed (ALE-controlled) and non-multiplexed configurations. |
| D0–D7 | Data bus | 8-bit bidirectional data path; compatible with 80C31, 80C251, and 68HC11 data bus timing. |
| RD, WR, CS | Control signals | Standard read/write/chip select strobes; enable direct connection to MCU control bus without external logic. |
| TCK, TMS, TDI, TDO | JTAG boundary-scan interface | IEEE 1149.1-compliant serial port on Port C pins; enables full-chip in-system programming and debug. |
| PC0–PC7 | Port C I/O | Configurable as JTAG signals, general I/O, or latched address outputs; PC0–PC3 serve dual role as Ready/Busy and status flags. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank Flash concurrency | Read from one bank while erasing/writing the other - enables zero-downtime firmware updates in field-deployed controllers. |
| Programmable PLD subsystem | 24 IMCs + 16 OMCs with Turbo Bit acceleration - implements custom chip selects, interrupt logic, and bus arbitration without external CPLDs. |
| Page register address expansion | 8-bit register maps 16-bit MCU address space to 24-bit effective range - eliminates need for external address latches in memory-constrained designs. |
| JTAG ISP with FlashLINK cable | Built-in IEEE 1149.1 port + low-cost PC interface - reduces manufacturing test/programming cost and enables post-solder reprogramming. |
| Open-drain I/O capability | 16 pins configurable as open-drain - supports wired-AND interrupt sharing, I²C-like signaling, and level translation to 3.3 V peripherals. |
Applications
| Industrial PLC I/O Expansion | Legacy MCU Memory Extension |
|---|---|
|
Use Scenario: Adding local program/data memory and custom I/O decoding to 80C51XA-based programmable logic controllers in factory automation cabinets. IC Role / Device Role / Timing Role: Acts as unified memory controller, PLD-based address decoder, and SRAM buffer - replacing multiple discrete chips on backplane daughterboards. Use Value: Reduces BOM count by 7+ components and eliminates timing skew between Flash, SRAM, and decode logic due to monolithic integration. |
Use Scenario: Extending address space and adding nonvolatile storage to 68HC11-based engine control units where ROM capacity is exhausted. IC Role / Device Role / Timing Role: Provides bank-switched Flash execution and page-register-expanded memory map - enabling legacy 16-bit MCU to access >1 MB of code space. Use Value: Avoids MCU upgrade; maintains software compatibility while supporting larger calibration tables and diagnostic routines. |
| Medical Instrument Bootloader | Test Equipment Firmware Manager |
|
Use Scenario: Hosting secure bootloader and field-upgradable firmware in portable ECG monitors using 80C251 microcontrollers. IC Role / Device Role / Timing Role: Stores protected boot code in secondary Flash and application in primary Flash - with JTAG-based secure ISP during service calibration. Use Value: Enables certified firmware updates without opening device enclosure; sector protection prevents accidental overwrite of safety-critical boot code. |
Use Scenario: Managing multi-version firmware images and instrument configuration data in automated PCB test handlers. IC Role / Device Role / Timing Role: Functions as programmable memory hub with PLD-based test pattern sequencing logic - synchronized to system clock via Turbo Bit. Use Value: Allows rapid test program switching via Flash sector selection; concurrent read/erase enables background image loading during active test cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Flash-based programmable peripheral applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD833F2-90J | 2 Mbit primary Flash (vs. 1 Mbit), same PLD/SRAM/JTAG specs; higher density but identical pinout and timing. | Required when firmware image size exceeds 1 Mbit; no change to PCB or driver software. | Select if future firmware growth is anticipated; drop-in replacement with no design modification. |
| PSD853F2-90J | Includes reset signal generation (RESET pin) and enhanced power management; otherwise identical memory/PLD architecture. | Suitable for systems requiring hardware reset coordination between MCU and peripheral; adds system-level reliability. | Choose when board-level reset sequencing must be integrated; requires minor schematic update for RESET net routing. |
Compared with PSD833F2-90J and PSD853F2-90J, the PSD813F2A-90J offers optimal cost/performance balance for fixed-size firmware deployments where extended Flash or reset integration is unnecessary - preserving design simplicity and minimizing component count.
Availability
PSD813F2A-90J is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, legacy MCU memory extension, and medical instrument bootloader applications requiring stable component supply and long-term lifecycle support.
Supply support for PSD813F2A-90J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, MCU, power, and memory solutions for industrial, automotive, and consumer markets.
The PSD8XXFX product line was developed specifically to replace discrete memory, logic, and interface components in 8-bit MCU systems - delivering integrated Flash, SRAM, PLD, and ISP capabilities in single-package solutions for cost-sensitive, space-constrained embedded designs.
FAQ
Is PSD813F2A-90J still in production?
No - PSD813F2A-90J is marked as Obsolete by STMicroelectronics per Doc ID 7833 Rev 7. However, Aetrix Electronics maintains legacy inventory with full traceability and offers extended lifecycle support, including obsolescence mitigation planning and cross-reference assistance for migration paths.
What JTAG tools are compatible with PSD813F2A-90J?
The device is fully compatible with ST's FlashLINK programming cable and associated PSDSoft development software. Third-party IEEE 1149.1-compliant JTAG emulators (e.g., Segger J-Link, Lauterbach TRACE32) can access boundary-scan but require custom configuration to support Flash erase/program commands via the JTAG instruction register.
Can the PLD logic be reconfigured independently of Flash contents?
Yes - the CPLD and DPLD logic blocks are programmed separately from Flash memory using distinct JTAG instructions. The PLD configuration is stored in on-chip EEPROM and retains state across power cycles, allowing logic updates without affecting firmware or SRAM data.
Does PSD813F2A-90J support 3 V operation?
No - PSD813F2A-90J is a 5 V-only device specified for VCC = 4.5 V to 5.5 V. It is not compatible with 3 V MCUs or mixed-voltage systems without level translation. ST's PSD8XXFX family includes 3 V variants (e.g., PSD813F2V), but those use different suffixes and are not pin-compatible.
PSD813F2A-90J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 52-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 52-PLCC (19.1x19.1)
- Grade:
- -
- Qualification:
- -
PSD813F2A-90J FAQ
1.How can I place an order for PSD813F2A-90J through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD813F2A-90J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD813F2A-90J reliable?
The price and inventory of PSD813F2A-90J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD813F2A-90J is usually 5 days.
3.What payment methods are accepted for PSD813F2A-90J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD813F2A-90J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD813F2A-90J?
PSD813F2A-90J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD813F2A-90J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD813F2A-90J?
For technical support, including PSD813F2A-90J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD813F2A-90J requirements.
6.How does Aetrix verify that PSD813F2A-90J is sourced from the original manufacturer or authorized distributors?
All PSD813F2A-90J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD813F2A-90J meets industry standards.
7.What is the process for return or replacement of PSD813F2A-90J?
All PSD813F2A-90J units undergo pre-shipment inspection (PSI). If there is an issue with PSD813F2A-90J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD813F2A-90J part is unused and in its original packaging.
Return procedure for PSD813F2A-90J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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