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STMicroelectronics PSD813F2A-90JI
- Part No.:
- PSD813F2A-90JI
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 52-LCC (J-Lead)
- Datasheet:
-
PSD813F2A-90JI.pdf
- Description:
- IC PROG PERIPH IC 52PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:1,996
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Product details
Overview
PSD813F2A-90JI from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (1 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, and a PLD with >3000 gates (16 OMCs/24 IMCs). It supports concurrent read-erase-write operations and is used in legacy industrial MCU systems requiring on-board firmware update capability and flexible address decoding.
For engineers reviewing the PSD813F2A-90JI datasheet, PSD813F2A-90JI pinout, PSD813F2A-90JI application, or PSD813F2A-90JI equivalent, key selection criteria include ISP JTAG interface compatibility, 5 V operation, PQFP52 package footprint, dual-bank Flash concurrency, and PLD-based chip select decoding for 8-bit bus interfacing.
Technical Context
The PSD813F2A-90JI implements a tightly coupled memory-peripheral architecture where the primary Flash (32K × 8, 8 uniform sectors) and secondary Flash (64K × 4, 4 uniform sectors) operate independently-enabling simultaneous execution from one bank while erasing/writing the other. Its page register expands MCU address space by 256× via internal banking logic.
The integrated PLD comprises two distinct blocks: a Decode PLD (DPLD) for user-defined chip-select decoding and a Complex PLD (CPLD) with 16 output macrocells supporting combinatorial or registered logic, both configurable via JTAG and accessible through dedicated control registers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Primary Flash | 1 Mbit (32K × 8), organized in 8 uniform sectors; enables firmware partitioning and safe over-the-air updates without halting execution. |
| Secondary Flash | 256 Kbit (64K × 4), 4 uniform sectors; provides dedicated storage for configuration data or boot code independent of main program memory. |
| SRAM | 256 Kbit (32K × 8); serves as high-speed data buffer or stack space for 8-bit MCUs with limited on-die RAM. |
| I/O Ports | 27 reconfigurable pins; support MCU I/O, PLD I/O, latched address output, or special functions-16 configurable as open-drain for wired-OR bus interfaces. |
| PLD Capacity | >3000 equivalent gates; includes 16 output macrocells (OMCs) and 24 input macrocells (IMCs) for custom logic implementation like address decoders or glue logic. |
| Programming Interface | JTAG-compliant serial port; enables full-chip in-system programming using low-cost FlashLINK cable-no external programmer required during manufacturing or field service. |
| Operating Voltage | 5 V ±10%; compatible with legacy 80C51, 80C251, 68HC11, and other 5 V microcontroller families without level-shifting. |
Pinout & Package
PSD813F2A-90JI is housed in a 52-pin Plastic Quad Flat Package (PQFP52), RoHS-compliant and ECOPACK® certified. Pin assignments follow STMicroelectronics' standard layout for the PSD8XXFX family, with dedicated JTAG (TCK/TMS/TDI/TDO), MCU bus interface (AD0–AD7, A8–A15, RD#, WR#, CS#), PLD I/O (PORTA–PORTD), and power/ground pins.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AD0–AD7 | Address/Data Multiplexed Bus | Bi-directional 8-bit bus shared between address (lower byte) and data; requires external latch (e.g., 74LS373) for demultiplexing in 80C51-style systems. |
| A8–A15 | Upper Address Bus | Dedicated non-multiplexed address lines enabling 64 KB addressing without external address latching overhead. |
| RD#, WR#, CS# | MCU Control Signals | Standard 8-bit bus strobes; CS# activates PSD device, RD#/WR# control read/write direction and timing alignment with MCU cycle. |
| TCK, TMS, TDI, TDO | JTAG Test Access Port | IEEE 1149.1-compliant interface for boundary-scan testing, in-system programming, and real-time debug access to internal registers and PLD configuration. |
| PORTA[0:7], PORTB[0:7], PORTC[0:7], PORTD[0:5] | Reconfigurable I/O Ports | 27 total pins individually assignable as MCU GPIO, PLD I/O, latched address outputs (e.g., A16–A23), or JTAG signals-configured via PCR and direction registers. |
Key Features
| Feature | Design Value |
|---|---|
| Concurrent Flash Operation | Read from primary Flash while erasing or programming secondary Flash-eliminates system stall during firmware updates. |
| Page Register Banking | Internal 8-bit page register extends 16-bit MCU address space to 24-bit (64 KB × 256 pages), enabling seamless access to >64 KB memory maps. |
| Dual PLD Architecture | Separate DPLD (chip-select decoder) and CPLD (logic engine) blocks allow independent configuration-DPLD handles memory mapping; CPLD implements custom state machines or protocol translators. |
| Programmable Power Management | Automatic Power-down (APD) unit reduces standby current to <100 µA; triggered by idle bus cycles or software command-extends battery life in portable industrial controllers. |
| Open-Drain I/O Capability | 16 I/O pins support open-drain mode with external pull-up; enables direct interface to I²C buses, interrupt lines, or shared control signals without discrete FETs. |
Applications
| Industrial PLC I/O Expansion | Legacy MCU Firmware Upgrade Module |
|---|---|
Use Scenario: Adding modular digital I/O to an 80C51-based programmable logic controller with fixed memory map. IC Role / Device Role / Timing Role: Acts as memory-mapped peripheral providing SRAM-backed I/O registers and PLD-decoded address windows for up to 256 discrete inputs/outputs. Use Value: Eliminates need for discrete address decoders and latch ICs; reduces BOM count by 4–6 components per module while enabling field-upgradable firmware. | Use Scenario: Enabling in-field firmware updates for medical infusion pumps using obsolete 80C251 microcontrollers. IC Role / Device Role / Timing Role: Serves as external Flash+SRAM+PLD subsystem that hosts new firmware images and executes them under MCU control via page register switching. Use Value: Supports zero-downtime firmware patching: new code runs from secondary Flash while primary Flash is erased and reprogrammed-no hardware reset required. |
| Automotive Body Control Unit (BCU) | Test Equipment Embedded Controller |
Use Scenario: Implementing customizable lighting sequence logic and sensor interface in a 68HC11-based vehicle body controller. IC Role / Device Role / Timing Role: CPLD block generates PWM timing for LED drivers; DPLD decodes CAN message ID ranges to trigger specific Flash-resident diagnostic routines. Use Value: Replaces 3–4 discrete logic ICs and EEPROM; allows post-production tuning of lighting behavior via JTAG-reprogrammable PLD configuration. | Use Scenario: Providing flexible signal routing and stimulus generation in automated test equipment with aging 80C31 host processors. IC Role / Device Role / Timing Role: Uses PLD to generate precise timing waveforms (e.g., SPI clock, UART start bits) and SRAM to buffer test vectors-offloading timing-critical tasks from the MCU. Use Value: Enables sub-100 ns pulse edge control and 32 KB pattern storage without modifying legacy 80C31 firmware-extending equipment service life by 5+ years. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Flash-based programmable peripheral applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD833F2-90JI | 2 Mbit primary Flash (vs. 1 Mbit), same 256 Kbit secondary Flash and PLD structure; identical PQFP52 package and pinout. | Supports larger firmware images and more complex PLD configurations; requires no PCB change but needs updated Flash programming toolchain. | Select when firmware size exceeds 1 Mbit or additional PLD logic resources are needed-drop-in replacement with higher memory density. |
| PSD853F2-90JI | Includes enhanced JTAG security features and extended sector protection registers; otherwise identical memory/PLD specs and package. | Required for applications needing secure firmware updates and tamper-resistant Flash locking-adds cryptographic key management overhead. | Choose only if regulatory compliance (e.g., IEC 62443) mandates Flash write-protection granularity beyond basic sector lock bits. |
Compared with PSD833F2-90JI and PSD853F2-90JI, the PSD813F2A-90JI offers optimal cost/performance balance for non-security-critical, mid-size firmware deployments-retaining full PLD functionality and JTAG ISP while minimizing memory overhead and licensing complexity.
Availability
PSD813F2A-90JI is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, legacy MCU firmware upgrade modules, and automotive body control units requiring stable component supply and long-term obsolescence mitigation.
Supply support for PSD813F2A-90JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management devices, and MEMS sensors for industrial, automotive, and consumer markets.
The PSD8XXFX product line was developed specifically to extend the lifespan of 8-bit MCU platforms by integrating Flash memory, SRAM, and programmable logic into a single ISP-capable peripheral-reducing design complexity and enabling field-upgradable embedded systems.
FAQ
What MCU families is the PSD813F2A-90JI officially supported for?
The PSD813F2A-90JI is validated for direct interface with 80C51XA, 80C251, 80C31, and 68HC11 microcontrollers. Its bus timing, control signal polarity, and address/data multiplexing modes match these families' native protocols-confirmed in Sections 15.5–15.8 of ST Doc ID 7833 Rev 7. No adapter logic is required for any of these MCUs.
Does the PSD813F2A-90JI support 3.3 V operation?
No-the PSD813F2A-90JI is a 5 V-only device specified for VCC = 4.5 V to 5.5 V (Table 40, Doc ID 7833 Rev 7). It lacks 3.3 V I/O tolerance and will not function reliably with 3.3 V MCU buses. For mixed-voltage systems, level-shifting circuitry or selection of the 3 V-compatible PSD8XXFX variants (e.g., PSD813F2V) is required.
How many times can the Flash memory be reprogrammed?
The primary and secondary Flash blocks are rated for a minimum of 10,000 erase/write cycles per sector (Section 9, Doc ID 7833 Rev 7). This endurance is guaranteed across the full industrial temperature range (–40 °C to +85 °C) and applies independently to each of the 12 total sectors (8 primary + 4 secondary).
Is JTAG debugging supported, or only programming?
JTAG on the PSD813F2A-90JI supports full IEEE 1149.1 boundary-scan testing and in-system programming only-not real-time CPU debugging. The JTAG port accesses internal configuration registers, PLD fuse maps, and Flash/SRAM contents, but does not provide visibility into or control over the host MCU's core state or registers.
PSD813F2A-90JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 52-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 52-PLCC (19.1x19.1)
- Grade:
- -
- Qualification:
- -
PSD813F2A-90JI FAQ
1.How can I place an order for PSD813F2A-90JI through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD813F2A-90JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD813F2A-90JI reliable?
The price and inventory of PSD813F2A-90JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD813F2A-90JI is usually 5 days.
3.What payment methods are accepted for PSD813F2A-90JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD813F2A-90JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD813F2A-90JI?
PSD813F2A-90JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD813F2A-90JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD813F2A-90JI?
For technical support, including PSD813F2A-90JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD813F2A-90JI requirements.
6.How does Aetrix verify that PSD813F2A-90JI is sourced from the original manufacturer or authorized distributors?
All PSD813F2A-90JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD813F2A-90JI meets industry standards.
7.What is the process for return or replacement of PSD813F2A-90JI?
All PSD813F2A-90JI units undergo pre-shipment inspection (PSI). If there is an issue with PSD813F2A-90JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD813F2A-90JI part is unused and in its original packaging.
Return procedure for PSD813F2A-90JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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