STMicroelectronics PSD813F2A-90U

Overview

PSD813F2A-90U from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (1 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, and a 3000-gate PLD with CPLD/DPLD architecture. It supports concurrent read/erase/write operations and features an enhanced JTAG port for ISP, page register for 256× address space expansion, and programmable power management - deployed in legacy industrial control systems interfacing with 80C51XA and 68HC11 MCUs.

For engineers reviewing the PSD813F2A-90U datasheet, PSD813F2A-90U pinout, PSD813F2A-90U application, or PSD813F2A-90U equivalent, this device requires verification of MCU bus timing compatibility (multiplexed/non-multiplexed 8-bit), PLD macrocell configuration (16 OMCs/24 IMCs), Flash sector protection settings, and JTAG ISP signal mapping (TCK/TMS/TDI/TDO on Port C).

Technical Context

The PSD813F2A-90U implements a tightly coupled memory-peripheral architecture where the primary Flash (32K × 8, 8 uniform sectors) and secondary Flash (64K × 4, 4 uniform sectors) operate concurrently under independent chip select logic. Its PLD subsystem comprises two distinct blocks: a Decode PLD (DPLD) for user-defined internal chip select decoding and a Complex PLD (CPLD) with 16 output macrocells and 24 input macrocells supporting combinatorial or registered logic.

Memory access is managed via a configurable MCU bus interface supporting both multiplexed (e.g., 80C51XA) and non-multiplexed (e.g., 68HC11) 8-bit buses, with dedicated signals including RD, WR, ALE, and CSI. The integrated page register enables 24-bit addressing by extending the MCU's 16-bit address bus through 8-bit page selection, while the JTAG port provides full-chip ISP without requiring external programming hardware.

Key Specifications

Pinout & Package

TQFP64 (U) package with 0.5 mm pitch, ECOPACK® compliant, 10 mm × 10 mm body size, and exposed thermal pad.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Flash+PLD peripheral applications.

Compared with PSD833F2-90U and PSD853F2-90U, the PSD813F2A-90U offers optimal cost/performance balance for mid-size firmware deployments where 1 Mbit Flash suffices and explicit reset signaling is unnecessary - preserving design simplicity and minimizing BOM cost.

Availability

PSD813F2A-90U is available at Aetrix Electronics and suitable for industrial PLC upgrades, legacy automotive ECU retrofits, and medical device bootloader platforms requiring stable component supply and long-term lifecycle support.

Supply support for PSD813F2A-90U includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, specializing in microcontrollers, power management, and embedded peripherals for industrial, automotive, and consumer markets.

The PSD8XXFX product line was designed specifically to replace discrete memory and logic components in 8-bit MCU systems - delivering integrated Flash, SRAM, PLD, and ISP capability in a single TQFP/PLCC package.

FAQ

What MCU families are natively supported by the PSD813F2A-90U?

The PSD813F2A-90U provides verified interface timing and control signal mapping for 80C51XA, 68HC11, 80C251, and 80C31 microcontrollers. Its MCU bus interface supports both multiplexed (address/data shared) and non-multiplexed (separate buses) configurations, with documented examples in Sections 15.5–15.8 of the datasheet. No FPGA or custom adapter is needed for these targets.

How does the dual-bank Flash architecture enable concurrent operations?

The PSD813F2A-90U separates primary and secondary Flash into independent memory blocks with dedicated chip select lines and status flags (e.g., Ready/Busy on PC3). This allows simultaneous read from one bank while erasing or programming the other - confirmed by the "Concurrent operation" feature in Section 1 and validated in Section 6.2 of the datasheet.

Can the PLD be reconfigured independently of Flash/SRAM contents?

Yes. The CPLD and DPLD logic configurations are stored in dedicated non-volatile registers within the PSD and can be modified via JTAG or MCU register writes without affecting Flash or SRAM data. Section 14 details loading procedures, and Table 16 specifies OMC bit assignments - enabling dynamic logic updates during system runtime.

Is the PSD813F2A-90U still in production or obsolete?

Per STMicroelectronics' official documentation (Doc ID 7833 Rev 7, May 2009), the PSD813F2A-90U is marked "Obsolete Product(s)" in Table 1 and throughout the document. However, Aetrix Electronics maintains active inventory and offers extended lifecycle support, including traceable batch sourcing and obsolescence mitigation planning for legacy design continuity.