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STMicroelectronics PSD833F2-90J
- Part No.:
- PSD833F2-90J
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 52-LCC (J-Lead)
- Datasheet:
-
PSD833F2-90J.pdf
- Description:
- IC PROG PERIPH IC 52PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:1,944
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Product details
Overview
PSD833F2-90J from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (1 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, JTAG ISP interface, and PLD logic (3000+ gates, 16 OMCs/24 IMCs). It operates at 5 V with 90 ns access time and supports concurrent read-erase-write operations in embedded MCU systems.
For engineers reviewing the PSD833F2-90J datasheet, PSD833F2-90J pinout, PSD833F2-90J application, or PSD833F2-90J equivalent, this device serves as a unified memory + logic + I/O expansion solution for legacy 80C51, 80C251, and 68HC11-based designs requiring in-field firmware updates, address space extension via page register, and custom chip-select decoding.
Technical Context
The PSD833F2-90J implements a tightly coupled architecture where the primary Flash (8 × 32K × 8) and secondary Flash (4 × 64K × 8) operate concurrently under independent control logic, enabling zero-wait-state reads during background erase/write. Its PLD subsystem comprises two distinct blocks: a Decode PLD (DPLD) for user-defined chip-select generation and a Complex PLD (CPLD) with 16 output macrocells supporting combinatorial or registered outputs.
Memory mapping is managed via an internal 8-bit page register that expands the MCU's 16-bit address space to 24 bits (256×), while the JTAG port (TCK/TMS/TDI/TDO on Port C pins) provides full boundary-scan and ISP capability without requiring external programming hardware beyond a low-cost FlashLINK cable.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Primary Flash | 1 Mbit (8 uniform 32K × 8 sectors); enables boot code + application storage with sector-level protection |
| Secondary Flash | 256 Kbit (4 uniform 64K × 8 sectors); used for data logging, parameter storage, or firmware backup |
| SRAM | 256 Kbit (32K × 8); provides fast, non-volatile-critical working memory accessible in same bus cycle as Flash |
| Access Time | 90 ns max; guarantees timing compatibility with 11.059 MHz 80C51 and 12 MHz 80C251 systems |
| I/O Ports | 27 pins; individually configurable as MCU I/O, PLD I/O, latched address outputs, or special function signals |
| PLD Capacity | 3000+ equivalent gates; includes 16 OMCs with programmable output enable and 24 IMCs for flexible glue logic |
| JTAG Interface | IEEE 1149.1-compliant; enables full-chip ISP, boundary-scan testing, and real-time debug without halting MCU operation |
Pinout & Package
PSD833F2-90J is housed in a 52-pin PLCC (Plastic Leaded Chip Carrier) package, ECOPACK® compliant, with 27 dedicated I/O pins distributed across Ports A–D and JTAG signals multiplexed on Port C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0–A7 | Address Bus Inputs | Accept lower 8 bits of MCU address bus; used for memory-mapped access to PSD registers and memory blocks |
| D0–D7 | Data Bus I/O | Bidirectional 8-bit data path; supports byte-wide transfers synchronized to RD/WR strobes |
| RD, WR | Read/Write Strobes | Active-low control signals defining data transfer direction and timing window for Flash/SRAM access |
| CSI (PD2) | Chip Select Input | Enables PSD only when asserted; allows multiple PSDs or peripherals on same bus with decoded CS |
| TCK, TMS, TDI, TDO | JTAG Serial Interface | Multiplexed on Port C pins (PC0–PC3); provide IEEE 1149.1 boundary-scan and in-system programming |
| RESET | Asynchronous Reset Input | Resets internal state machines, PLD registers, and memory controllers; does not erase Flash contents |
Key Features
| Feature | Design Value |
|---|---|
| Concurrent Memory Operation | Read from primary Flash while erasing/writing secondary Flash - eliminates system stall during firmware update |
| Page Register Address Expansion | 8-bit internal register extends 16-bit MCU address bus to 24-bit space (64 KB → 16 MB), enabling seamless bank switching |
| Dual PLD Architecture | DPLD handles dynamic chip-select decoding; CPLD implements custom logic (e.g., interrupt arbitration, bus buffering) with 16 OMCs |
| Open-Drain I/O Capability | 16 of 27 I/Os configurable as open-drain - supports wired-AND interrupt lines and I²C-compatible signaling |
| Programmable Power Management | Automatic Power-down (APD) unit reduces current to <100 µA in standby; configurable wake-up sources include RD/WR edges |
Applications
| Industrial PLC I/O Expansion | Legacy MCU Firmware Upgrade System |
|---|---|
Use Scenario: Adding isolated digital I/O, analog monitoring, and local logic to 80C51-based PLC controllers without redesigning main board. IC Role / Device Role / Timing Role: Acts as memory-mapped peripheral providing SRAM buffer, Flash-stored configuration tables, and CPLD-generated control signals for relay drivers and sensor interfaces. Use Value: Eliminates discrete glue logic and external EEPROM; enables field-upgradable ladder logic via JTAG without removing controller from panel. | Use Scenario: Enabling over-the-air or USB-host-initiated firmware updates in medical infusion pumps using 80C251 MCU. IC Role / Device Role / Timing Role: Hosts dual-bank Flash where active firmware runs from primary bank while new version is verified and written to secondary bank. Use Value: Achieves zero-downtime updates with atomic swap via page register reconfiguration - no bootloader required in MCU ROM. |
| Automotive Body Control Module | Test Equipment Embedded Controller |
Use Scenario: Managing door lock actuators, window lifters, and mirror controls in 68HC11-based BCMs with strict EMI and power constraints. IC Role / Device Role / Timing Role: Provides PLD-decoded chip selects for CAN transceiver, LIN interface, and EEPROM; uses SRAM for real-time status shadowing. Use Value: Reduces BOM count by replacing 74-series logic and discrete address decoders; APD mode cuts quiescent current below 50 µA during sleep. | Use Scenario: Serving as programmable logic and memory hub in automated test fixtures for PCB functional validation. IC Role / Device Role / Timing Role: Stores test vectors in Flash, buffers results in SRAM, and generates custom timing strobes (e.g., SPI clock dividers, pulse-width modulators) via CPLD. Use Value: Enables rapid test script changes without FPGA recompilation; JTAG ISP allows fixture calibration data updates without opening enclosure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Flash+PLD+SRAM peripheral applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD834F2-90J | Same architecture but with 2 Mbit primary Flash (vs. 1 Mbit); identical pinout and timing | Required when larger boot/application image size exceeds 1 Mbit capacity | Select only if additional Flash density is needed; otherwise, PSD833F2-90J offers optimal cost/performance balance |
| PSD853F2-90J | Includes enhanced power management (lower APD current) and extended temperature range (−40°C to +105°C vs. −40°C to +85°C) | Suitable for automotive under-hood or industrial high-temp environments where thermal margin is critical | Choose for extended temperature operation; not recommended for standard commercial applications due to higher cost |
Compared with PSD834F2-90J and PSD853F2-90J, the PSD833F2-90J delivers the most cost-effective integration of Flash, SRAM, and PLD for standard-temperature 8-bit MCU systems requiring 1 Mbit primary code storage and concurrent memory operations.
Availability
PSD833F2-90J is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, legacy MCU firmware upgrade systems, and automotive body control modules requiring stable component supply and long-term lifecycle support.
Supply support for PSD833F2-90J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management devices, and memory solutions for industrial, automotive, and consumer markets.
The PSD8XXFX product line was developed specifically to replace discrete memory, logic, and interface components in 8-bit MCU systems - delivering integrated Flash, SRAM, PLD, and JTAG ISP in a single PLCC or TQFP package.
FAQ
Is PSD833F2-90J still in production?
No - PSD833F2-90J is marked as Obsolete by STMicroelectronics per Doc ID 7833 Rev 7. However, Aetrix Electronics maintains legacy inventory with full traceability and offers extended lifecycle support, including obsolescence mitigation planning and cross-reference guidance for migration paths.
What MCU families are directly supported?
The PSD833F2-90J natively interfaces with 80C31, 80C251, 80C51XA, and 68HC11 MCUs via documented bus timing and control signal mappings. Its MCU bus interface supports both multiplexed (AD0–AD7) and non-multiplexed (A0–A7/D0–D7) configurations without external logic.
Can the PLD logic be reprogrammed in-system?
Yes - the CPLD and DPLD blocks are fully reprogrammable via the JTAG interface without requiring device removal. Configuration bitstreams are stored in Flash and automatically loaded at power-up; JTAG allows live modification during system operation for debugging or dynamic reconfiguration.
Does the 90 ns access time apply to all memory types?
Yes - the 90 ns maximum access time applies uniformly to primary Flash, secondary Flash, and SRAM when operated within specified 5 V ±10% supply and 0°C to +85°C ambient conditions. SRAM retains full-speed random access; Flash read cycles meet this spec under standard read command sequences.
PSD833F2-90J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 52-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 52-PLCC (19.1x19.1)
- Grade:
- -
- Qualification:
- -
PSD833F2-90J FAQ
1.How can I place an order for PSD833F2-90J through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD833F2-90J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD833F2-90J reliable?
The price and inventory of PSD833F2-90J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD833F2-90J is usually 5 days.
3.What payment methods are accepted for PSD833F2-90J?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD833F2-90J transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD833F2-90J?
PSD833F2-90J orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD833F2-90J order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD833F2-90J?
For technical support, including PSD833F2-90J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD833F2-90J requirements.
6.How does Aetrix verify that PSD833F2-90J is sourced from the original manufacturer or authorized distributors?
All PSD833F2-90J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD833F2-90J meets industry standards.
7.What is the process for return or replacement of PSD833F2-90J?
All PSD833F2-90J units undergo pre-shipment inspection (PSI). If there is an issue with PSD833F2-90J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD833F2-90J part is unused and in its original packaging.
Return procedure for PSD833F2-90J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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