STMicroelectronics PSD834F2-90M

Overview

PSD834F2-90M from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (1 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, and PLD logic (3000+ gates, 16 OMCs/24 IMCs) in a single PQFP52 package. It enables memory expansion, address decoding, and glue logic replacement in legacy 80C51/80C251/68HC11-based embedded systems.

For engineers reviewing the PSD834F2-90M datasheet, PSD834F2-90M pinout, PSD834F2-90M application, or PSD834F2-90M equivalent, this device serves as a unified memory + logic solution for space-constrained 5 V MCU designs requiring concurrent Flash read/erase, page register–based address extension, and JTAG-programmable CPLD/DPLD functionality.

Technical Context

The PSD834F2-90M implements a tightly coupled architecture where the primary Flash (32K × 8, 8 uniform sectors) and secondary Flash (64K × 4, 4 uniform sectors) operate concurrently-enabling read-from-one-bank while erasing/writing the other. Its PLD subsystem comprises two independent blocks: a Decode PLD (DPLD) for user-defined chip-select decoding and a Complex PLD (CPLD) with 16 output macrocells supporting combinatorial or registered outputs.

Memory access is managed via an 8-bit multiplexed or non-multiplexed MCU bus interface, with dedicated control signals (e.g., RD, WR, CSI, PC3 Ready/Busy) and a 8-bit page register that extends the MCU's address space by 256×. Power management includes Automatic Power-down (APD) mode triggered by idle bus cycles, reducing current to 10 µA typical in standby.

Key Specifications

Pinout & Package

PQFP52 (Plastic Quad Flat Package, 52-pin, 0.65 mm pitch), RoHS-compliant ECOPACK® package. Pin assignments conform to Appendix A of Doc ID 7833 Rev 7.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Flash+PLD peripheral applications.

Compared with PSD833F2-90M, the PSD834F2-90M doubles primary Flash capacity for robust dual-bank firmware updates; versus PSD854F2-90M, it retains PQFP52 compatibility while delivering sufficient memory for most 8051-based industrial controllers - optimizing upgrade path and footprint reuse.

Availability

PSD834F2-90M is available at Aetrix Electronics and suitable for industrial PLCs, legacy medical device upgrades, and automotive body control units requiring stable component supply across extended product lifecycles.

Supply support for PSD834F2-90M includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog/mixed-signal devices for industrial, automotive, and consumer markets.

The PSD8XXFX family was engineered specifically to extend the lifespan of 8-bit MCU platforms by integrating Flash memory, SRAM, and programmable logic into a single, JTAG-programmable peripheral - targeting cost-sensitive, long-lifecycle embedded systems where FPGA complexity is unjustified.

FAQ

Is PSD834F2-90M still in production?

No - STMicroelectronics has marked the PSD834F2-90M as obsolete (per Doc ID 7833 Rev 7, Table 1). However, Aetrix Electronics maintains legacy inventory with full traceability and offers extended lifecycle support, including obsolescence forecasting, cross-reference assistance, and last-time-buy coordination for ongoing production programs.

What development tools support PSD834F2-90M programming?

ST's original FlashLINK JTAG programmer and PSDSoft development suite (v3.x) are fully compatible. Aetrix provides validated toolchain bundles including USB-to-JTAG adapters, pre-configured PSDSoft license keys, and reference scripts for Intel Hex file loading - all tested against the 90 MHz timing spec and PQFP52 pinout.

Can the PLD logic be reprogrammed in the field?

Yes - both CPLD and DPLD configurations are stored in the secondary Flash memory and can be updated via JTAG ISP without removing the device from the PCB. The PLD bitstream is loaded at power-up or reset, and reprogramming takes <2 seconds with standard FlashLINK hardware.

Does PSD834F2-90M support 3.3 V operation?

No - the "-90M" suffix denotes a 5 V-only device (confirmed in Table 40, "Operating conditions (5 V devices)" of Doc ID 7833 Rev 7). It is not 3.3 V tolerant; applying 3.3 V to VCC will prevent proper Flash programming and PLD configuration loading. For mixed-voltage systems, level-shifting buffers are required on I/O lines.