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STMicroelectronics PSD835G2-70U
- Part No.:
- PSD835G2-70U
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 80-LQFP
- Datasheet:
-
PSD835G2-70U.pdf
- Description:
- IC PROG PERIPH IC 80LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:3,058
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Product details
Overview
PSD835G2-70U from STMicroelectronics is a programmable system device (PSD) integrating 4 Mbit + 256 Kbit dual Flash memory, 64 Kbit SRAM, CPLD/DPLD logic (3000+ gates), and 52 reconfigurable I/O ports - all in a single LQFP80 package for 8-bit MCU systems. It supports concurrent read/erase/write operations, in-system programming via JTAG, and page register–based address expansion. Used in legacy industrial controllers and embedded instrumentation requiring nonvolatile code storage, local logic customization, and memory-mapped peripheral interfacing.
For engineers reviewing the PSD835G2-70U datasheet, PSD835G2-70U pinout, PSD835G2-70U application, or PSD835G2-70U equivalent, key selection considerations include Flash bank concurrency, PLD macrocell count (16 OMCs + 24 IMCs), 70 ns memory access timing at 5 V, JTAG ISP capability, and compatibility with 80C51/80C251/68HC11 buses.
Technical Context
The PSD835G2-70U implements a tightly coupled architecture where Flash, SRAM, and PLD blocks share a unified 8-bit MCU bus interface with configurable chip select decoding. Its dual-bank Flash enables simultaneous execution from one bank while reprogramming the other - critical for firmware updates without system halt.
Two distinct PLD subsystems coexist: a user-configurable Decode PLD (DPLD) for internal chip select generation, and a Complex PLD (CPLD) with 16 output macrocells (OMCs) and 24 input macrocells (IMCs) supporting combinatorial and registered logic. The integrated page register extends the MCU's 16-bit address space by 8-bit page selection, enabling up to 16 MB of effective memory mapping.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Architecture | Dual-bank Flash (4 Mbit primary + 256 Kbit secondary) + 64 Kbit SRAM - enables concurrent read/erase/write for zero-downtime firmware updates. |
| Access Time | 70 ns at VCC = 4.5–5.5 V - guarantees deterministic timing for 8-bit MCUs running ≤14 MHz with wait-state–free operation. |
| PLD Capacity | 3000+ equivalent gates; 16 OMCs + 24 IMCs - sufficient for glue logic replacement, address decoding, and custom peripheral control in compact designs. |
| I/O Count | 52 individually configurable pins - supports mixed-mode usage: MCU data/address lines, PLD I/O, latched address outputs, and JTAG signals on Port E. |
| Programming Interface | JTAG-compliant ISP port - allows full-chip in-system programming using low-cost FlashLINK cable; eliminates need for socketed programming fixtures. |
| Power Management | Standby current ≤50 µA; Automatic Power-down (APD) unit - extends battery life in intermittently active embedded systems. |
| Data Retention | 15 years - ensures long-term reliability for firmware and configuration data in unattended industrial deployments. |
Pinout & Package
LQFP80 (U) package: 80-pin, 12 × 12 mm body, 0.5 mm pitch, exposed thermal pad (not electrically connected). Pin assignments conform to STMicroelectronics' PSD835G2 pinout specification (Rev 5, Appendix A).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply / Ground | Single 5 V ±10% supply; dedicated power/ground pairs per quadrant reduce noise coupling in mixed-signal operation. |
| A0–A15, D0–D7 | Address/Data bus | Standard 8-bit multiplexed or non-multiplexed interface compatible with 80C51, 80C251, and 68HC11 families. |
| RD, WR, CS, OE, WE | Control signals | Configurable active-low strobes; support both standard and custom timing modes via internal register settings. |
| TCK, TMS, TDI, TDO | JTAG ISP interface | Located on Port E pins (PE0–PE3); enable boundary-scan testing and full-chip reprogramming without MCU involvement. |
| RESET | Asynchronous reset input | Active-low signal that initializes Flash state machines, PLD registers, and I/O direction controls - synchronized to internal clock domain. |
Key Features
| Feature | Design Value |
|---|---|
| Concurrent Flash Operation | Read from primary bank while erasing/writing secondary bank - eliminates firmware update stalls in real-time control loops. |
| Page Register Address Expansion | 8-bit internal page register multiplies 64 KB MCU address space by 256 → 16 MB effective addressing - replaces external latch logic. |
| PLD Flexibility | DPLD handles chip-select decoding; CPLD implements custom logic - both configured via JTAG, enabling late-stage hardware changes without PCB revision. |
| Open-Drain I/O Support | 52 ports configurable as open-drain - permits wired-AND bus arbitration, level translation, and direct connection to legacy peripherals like I²C or interrupt lines. |
| Flash Endurance | 100,000 erase/write cycles - supports field-upgradable firmware in devices deployed for >10 years with frequent OTA updates. |
Applications
| Industrial PLC I/O Module | Legacy MCU-Based Test Equipment |
|---|---|
Use Scenario: Compact programmable logic controller with isolated digital I/O, analog monitoring, and firmware-upgradable control algorithms. IC Role / Device Role / Timing Role: Central memory and logic hub - hosts boot code in primary Flash, stores calibration tables in secondary Flash, executes real-time tasks from SRAM, and decodes I/O address ranges via DPLD. Use Value: Eliminates discrete EPROM, SRAM, and PAL chips; reduces BOM count by 7+ components while enabling in-field firmware patches without hardware change. |
Use Scenario: Benchtop multimeter or signal generator using 80C51 microcontroller, requiring nonvolatile storage for user configurations and waveform data. IC Role / Device Role / Timing Role: Memory and interface accelerator - provides 70 ns SRAM for fast register access, dual Flash for separate program/data storage, and PLD-based trigger logic synchronization. Use Value: Enables combined program/data space mode per 80C51XA spec; removes wait states during waveform buffer reads; simplifies front-panel button debouncing with CPLD logic. |
| Automotive Diagnostic Tool | Medical Sensor Hub |
Use Scenario: Handheld OBD-II scanner interfacing with multiple vehicle ECUs via UART/CAN, storing protocol stacks and diagnostic codes. IC Role / Device Role / Timing Role: Firmware repository and protocol engine - primary Flash holds bootloader and ISO-TP stack; secondary Flash stores vehicle-specific DTC databases; PLD manages UART FIFO handshaking. Use Value: Concurrent Flash operation allows background DTC database updates while scanner remains operational; JTAG ISP enables factory reflash without disassembly. |
Use Scenario: Portable patient monitor aggregating ECG, SpO₂, and temperature data, with local storage and USB upload capability. IC Role / Device Role / Timing Role: Data co-processor and memory manager - SRAM buffers sensor streams; secondary Flash logs timestamped events; page register enables seamless switching between acquisition and analysis memory banks. Use Value: 50 µA standby current extends battery life during idle periods; open-drain I/O safely interfaces with analog front-end ICs operating at different voltage domains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable system device applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD813F2-70U | Smaller memory (2 Mbit + 128 Kbit Flash, 32 Kbit SRAM); same PLD structure and pinout. | Suitable for cost-sensitive designs with reduced firmware footprint and fewer configuration parameters. | Select when total memory requirement is <3 Mbit and BOM cost optimization is prioritized over future firmware scalability. |
| PSD834F2-70U | Same memory size but lacks secondary Flash bank - single 4 Mbit Flash only; no concurrent operation capability. | Applicable where firmware updates occur only during maintenance windows and runtime continuity is not required. | Choose only if dual-bank Flash concurrency is unnecessary and legacy design reuse mandates identical PLD resources without added complexity. |
Compared with PSD835G2-70U, PSD813F2-70U trades memory capacity for lower unit cost, while PSD834F2-70U sacrifices concurrent Flash operation - making PSD835G2-70U the sole option supporting live firmware updates in resource-constrained 8-bit systems.
Availability
PSD835G2-70U is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy MCU-based test equipment, and automotive diagnostic tools requiring stable component supply across extended product lifecycles.
Supply support for PSD835G2-70U includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power ICs, sensors, and programmable logic devices for industrial, automotive, and consumer markets.
The PSD (Programmable System Device) product line was developed to integrate Flash memory, SRAM, and configurable logic into a single chip for 8-bit MCU systems - reducing board space, improving reliability, and enabling post-manufacture hardware customization.
FAQ
Is PSD835G2-70U still in production?
No - PSD835G2-70U is marked as Obsolete by STMicroelectronics (per Rev 5 datasheet cover). However, Aetrix Electronics maintains legacy inventory and offers controlled-life supply support, including last-time buy coordination and cross-reference assistance for migration paths.
What development tools are required for programming?
PSDsoft™ software (v3.x or later) is mandatory for configuring PLD logic, generating Flash images, and setting register maps. Programming requires a JTAG interface - ST's FlashLINK cable (or compatible IEEE 1149.1-compliant adapter) connected to a Windows PC running PSDsoft™.
Can the PLD logic be reconfigured independently of Flash contents?
Yes - the CPLD and DPLD logic are stored in dedicated configuration Flash sectors and can be updated separately from application code. PSDsoft™ allows incremental PLD bitstream downloads without erasing primary Flash firmware or SRAM data.
Does it support 3.3 V operation?
No - PSD835G2-70U is specified only for 5 V ±10% operation (4.5–5.5 V). Its I/Os are not 3.3 V tolerant; interfacing with 3.3 V MCUs requires level-shifting circuitry or voltage translators on address/data/control lines.
PSD835G2-70U Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 80-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 80-LQFP (12x12)
- Grade:
- -
- Qualification:
- -
PSD835G2-70U FAQ
1.How can I place an order for PSD835G2-70U through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD835G2-70U on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD835G2-70U reliable?
The price and inventory of PSD835G2-70U are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD835G2-70U is usually 5 days.
3.What payment methods are accepted for PSD835G2-70U?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD835G2-70U transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD835G2-70U?
PSD835G2-70U orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD835G2-70U order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD835G2-70U?
For technical support, including PSD835G2-70U datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD835G2-70U requirements.
6.How does Aetrix verify that PSD835G2-70U is sourced from the original manufacturer or authorized distributors?
All PSD835G2-70U products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD835G2-70U meets industry standards.
7.What is the process for return or replacement of PSD835G2-70U?
All PSD835G2-70U units undergo pre-shipment inspection (PSI). If there is an issue with PSD835G2-70U, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD835G2-70U part is unused and in its original packaging.
Return procedure for PSD835G2-70U:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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