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STMicroelectronics PSD835G2-90U
- Part No.:
- PSD835G2-90U
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 80-LQFP
- Datasheet:
-
PSD835G2-90U.pdf
- Description:
- IC PROG PERIPH IC 80LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:1,780
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Product details
Overview
PSD835G2-90U from STMicroelectronics is a programmable system device (PSD) integrating 4 Mbit + 256 Kbit dual Flash memory, 64 Kbit SRAM, CPLD/DPLD logic (3000+ gates), and 52 reconfigurable I/O ports - all in a single LQFP80 package for 8-bit MCU systems. It supports concurrent read/erase/write operations, in-system programming via JTAG, and page register–based address expansion for legacy 80C51/80C251/68HC11 platforms.
For engineers reviewing the PSD835G2-90U datasheet, PSD835G2-90U pinout, PSD835G2-90U application, or PSD835G2-90U equivalent, key selection criteria include dual-bank Flash concurrency, PLD-based chip select decoding, JTAG ISP capability, and 5 V±10% operation with 90 ns memory access timing.
Technical Context
The PSD835G2-90U implements a tightly coupled architecture where Flash, SRAM, and PLD blocks share a unified 8-bit MCU bus interface with configurable sector protection, suspend/resume erase, and data polling/toggle status flags. Its memory subsystem includes uniform 64 KB primary Flash sectors and four 64 KB secondary Flash sectors, enabling firmware partitioning and field updates without halting execution.
The integrated PLD comprises two independent units: a 16-output macrocell CPLD for glue logic and I/O control, and a user-configurable DPLD for internal chip select decoding - both supporting reprogrammability and synchronized with the MCU's RD/WR strobes and address latching modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Configuration | 4 Mbit primary Flash (8 × 64 KB sectors) + 256 Kbit secondary Flash (4 × 64 KB sectors) + 64 Kbit SRAM - enables concurrent read/erase/write across banks for real-time firmware update. |
| Access Time | 90 ns at VCC = 4.5–5.5 V - defines maximum MCU bus clock rate for reliable read/write cycles without wait states. |
| PLD Capacity | Over 3000 equivalent gates with 16 OMCs and 24 IMCs - supports custom address decoding, peripheral enable logic, and I/O direction control without external glue logic. |
| JTAG ISP Support | Fully compliant IEEE 1149.1 interface with FlashLINK cable compatibility - eliminates need for dedicated programming hardware during manufacturing or field service. |
| Power Management | Standby current ≤ 50 µA and Automatic Power-down (APD) unit - extends battery life in low-duty-cycle embedded controllers. |
| I/O Flexibility | 52 individually configurable pins supporting MCU I/O, PLD I/O, latched address output, or open-drain mode - simplifies board layout and reduces external level-shifting components. |
| Data Retention | 15 years minimum for Flash and PLD configuration - ensures long-term reliability in industrial temperature-grade applications. |
Pinout & Package
LQFP80 (U) package with 80-pin quad flat profile, ECOPACK® compliant, 10 mm × 10 mm body, 0.5 mm pitch. Pin assignments validated per STMicroelectronics datasheet Rev 5 Appendix A (Pin Assignments, pp. 118–119).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power Supply | 5 V ±10% main supply for all internal blocks; decoupling required within 1 cm of pin. |
| GND | Ground Reference | Dedicated analog/digital ground plane connection point; multiple GND pins ensure low-impedance return path. |
| RD, WR | MCU Control Strobes | Synchronize Flash/SRAM read/write cycles with 8-bit MCU bus timing; compatible with 80C51, 80C251, 68HC11. |
| ALE | Address Latch Enable | Triggers latching of lower address byte on Port A/B/C for multiplexed bus interfaces. |
| TCK, TMS, TDI, TDO | JTAG Interface | Enable full-chip in-system programming and boundary-scan testing via Port E pins (E0–E3). |
| CSI (PD2) | Chip Select Input | Active-low enable signal for PSD memory mapping; used by DPLD to generate internal CS signals for peripherals. |
| PE4 (Ready/Busy) | Status Output | Indicates Flash programming/erase completion or busy state; used for polling-based synchronization. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank Flash concurrency | Enables simultaneous READ from one bank while ERASE/WRITE executes in the other - critical for fail-safe firmware upgrades. |
| Page register (256× address expansion) | Extends 16-bit MCU address space to 24-bit range using software-controlled page latch - eliminates need for external address multiplexers. |
| PLD-based chip select decoding | DPLD block generates up to 8 independent chip selects from decoded address bits - replaces discrete logic for peripheral interfacing. |
| In-application programming (IAP) | Allows Flash reprogramming during MCU runtime via dedicated command sequences - supports over-the-air update mechanisms. |
| Open-drain I/O configuration | 52 pins support open-drain mode with programmable pull-up - enables wired-AND bus arbitration and I²C-compatible signaling. |
Applications
| Industrial PLC I/O Module | Legacy 8051-Based Medical Device |
|---|---|
Use Scenario: Compact programmable logic controller with isolated digital I/O, sensor interface, and firmware update capability. IC Role / Device Role / Timing Role: Acts as memory + logic hub: maps MCU address space to I/O registers, decodes peripheral CS lines, and stores boot/firmware images in protected Flash sectors. Use Value: Reduces BOM count by replacing discrete EPROM, SRAM, and PAL devices; 90 ns access time meets deterministic scan cycle timing. |
Use Scenario: Portable patient monitor requiring long-life battery operation, secure firmware storage, and field-upgradable calibration tables. IC Role / Device Role / Timing Role: Provides nonvolatile program/data memory, power-managed SRAM retention, and JTAG-accessible Flash for regulatory-compliant reprogramming. Use Value: 50 µA standby current extends battery runtime; 15-year data retention satisfies medical device lifecycle requirements. |
| Automotive Body Control Unit | Smart Energy Meter Controller |
Use Scenario: Low-cost ECU managing door locks, lighting, and CAN gateway functions using 8-bit MCU. IC Role / Device Role / Timing Role: Integrates Flash firmware storage, SRAM working memory, and PLD-based wake-up logic triggered by LIN or discrete inputs. Use Value: Concurrent Flash operation allows background firmware validation while executing real-time control tasks. |
Use Scenario: Electricity meter with tamper detection, tariff switching, and metrology data logging. IC Role / Device Role / Timing Role: Stores encrypted firmware, calibration constants, and usage logs in sector-protected Flash; uses PLD to gate metering interrupt sources. Use Value: 100,000 Flash endurance supports >10 years of daily firmware patching; ECOPACK® package meets RoHS compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable memory + logic integration applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD813F2-90U | Smaller memory: 2 Mbit + 128 Kbit Flash, 32 Kbit SRAM; same PLD architecture and pinout. | Suitable for cost-sensitive designs with reduced firmware footprint and fewer peripherals. | Select when total memory requirement is ≤2.128 Mbit and BOM cost optimization is prioritized over future scalability. |
| PSD833G2-90U | Identical memory size and PLD capacity but lacks secondary Flash bank - no concurrent erase/write capability. | Applicable where firmware updates occur only during maintenance windows, not real-time operation. | Choose only if dual-bank concurrency is unnecessary and legacy design reuse mandates identical feature set minus secondary Flash. |
Compared with PSD835G2-90U, PSD813F2-90U trades memory headroom for lower unit cost, while PSD833G2-90U sacrifices concurrent Flash operation - making PSD835G2-90U the sole option supporting live firmware patching in resource-constrained 8-bit systems.
Availability
PSD835G2-90U is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy 8051-based medical devices, and automotive body control units requiring stable component supply amid obsolescence management.
Supply support for PSD835G2-90U includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, power management, and programmable logic solutions for industrial, automotive, and consumer markets.
The PSD (Programmable System Device) product line was designed to replace discrete memory and glue logic in 8-bit MCU systems - delivering integrated Flash, SRAM, and reconfigurable PLD functionality in a single, JTAG-programmable package.
FAQ
Is PSD835G2-90U still in production?
No - PSD835G2-90U is marked "Obsolete Product(s)" in STMicroelectronics' official documentation (Rev 5, Feb 2009). However, Aetrix Electronics maintains legacy inventory with full traceability and offers extended lifecycle support including cross-reference assistance and last-time-buy planning for ongoing production programs.
What development tools are required for programming?
PSD835G2-90U requires ST's PSDsoft™ design suite (v3.x or later) for PLD configuration, memory mapping, and JTAG programming. Hardware interface uses the FlashLINK cable (ST part number FLK-CBL) connected to a standard PC parallel port or USB-to-parallel adapter with compatible drivers.
Can it interface directly with an 80C51 without address latching?
Yes - the PSD835G2-90U supports non-multiplexed 8-bit bus mode (described in Section 16.2 of the datasheet), accepting separate AD0–AD7, A8–A15, and control signals (RD/WR/CS) - eliminating need for external address latches when paired with enhanced 80C51 variants like 80C51XA.
How is Flash sector protection configured?
Flash sector protection is controlled via dedicated status registers (address offsets 0x0000–0x0003) accessible through the MCU bus. Each 64 KB sector has individual lock bits; protection is enabled/disabled using specific unlock sequences and verified via Read Sector Protection Status instruction (see Section 7.5).
PSD835G2-90U Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 80-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 80-LQFP (12x12)
- Grade:
- -
- Qualification:
- -
PSD835G2-90U FAQ
1.How can I place an order for PSD835G2-90U through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD835G2-90U on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD835G2-90U reliable?
The price and inventory of PSD835G2-90U are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD835G2-90U is usually 5 days.
3.What payment methods are accepted for PSD835G2-90U?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD835G2-90U transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD835G2-90U?
PSD835G2-90U orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD835G2-90U order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD835G2-90U?
For technical support, including PSD835G2-90U datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD835G2-90U requirements.
6.How does Aetrix verify that PSD835G2-90U is sourced from the original manufacturer or authorized distributors?
All PSD835G2-90U products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD835G2-90U meets industry standards.
7.What is the process for return or replacement of PSD835G2-90U?
All PSD835G2-90U units undergo pre-shipment inspection (PSI). If there is an issue with PSD835G2-90U, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD835G2-90U part is unused and in its original packaging.
Return procedure for PSD835G2-90U:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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