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STMicroelectronics PSD835G2-90UI
- Part No.:
- PSD835G2-90UI
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 80-LQFP
- Datasheet:
-
PSD835G2-90UI.pdf
- Description:
- IC PROG PERIPH IC 80LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:2,311
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Product details
Overview
PSD835G2-90UI from STMicroelectronics is a programmable system device (PSD) integrating 4 Mbit + 256 Kbit dual Flash memory, 64 Kbit SRAM, CPLD/DPLD logic (3000+ gates), and 52 reconfigurable I/O ports - all in a single LQFP80 package for 8-bit MCU systems. It supports concurrent read/erase/write operations, in-system programming via JTAG, and page register–based address expansion for legacy 80C51/80C251/68HC11 platforms.
For engineers reviewing the PSD835G2-90UI datasheet, PSD835G2-90UI pinout, PSD835G2-90UI application, or PSD835G2-90UI equivalent, key selection criteria include dual-bank Flash concurrency, PLD-based chip select decoding, JTAG ISP capability, and 90 ns access timing under 5 V ±10% supply - critical for embedded control, industrial HMI, and legacy MCU upgrade designs.
Technical Context
The PSD835G2 implements a tightly coupled architecture where Flash memory banks are independently accessible: primary Flash (4 Mbit, 8 uniform 64 KB sectors) and secondary Flash (256 Kbit, 4 sectors), enabling simultaneous READ from one bank while erasing/writing the other. Its PLD subsystem comprises two distinct blocks - a 16-output-macrocell CPLD and a user-configurable DPLD for internal chip select decoding - both programmable via JTAG.
Memory interface operates in multiplexed or non-multiplexed 8-bit bus modes compatible with 80C31, 80C251, 80C51XA, and 68HC11 MCUs. The integrated page register expands MCU address space by 256×, and the Power Management Unit enables automatic power-down with standby current as low as 50 µA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Flash Memory | 4 Mbit primary + 256 Kbit secondary; enables concurrent read/erase/write for firmware updates without system halt |
| SRAM | 64 Kbit on-chip; eliminates need for external RAM in compact 8-bit MCU designs |
| Access Time | 90 ns at VCC = 4.5–5.5 V; meets timing requirements of 80C51 derivatives running ≤11 MHz |
| PLD Capacity | 3000+ equivalent gates; includes 16-output CPLD and user-defined DPLD for flexible peripheral decoding |
| I/O Ports | 52 individually configurable pins; supports MCU I/O, PLD I/O, latched address output, and open-drain mode |
| Programming Interface | JTAG-compliant ISP port; enables in-circuit programming using low-cost FlashLINK cable and PSDsoft™ |
| Endurance | 100,000 Flash erase/write cycles; ensures long-term field reliability in update-intensive applications |
| Package | LQFP80 (U); RoHS-compliant ECOPACK® package with 0.5 mm pitch, suitable for automated SMT assembly |
Pinout & Package
LQFP80 (U) package with 80-pin quad flat profile, 0.5 mm lead pitch, and exposed thermal pad per STMicroelectronics mechanical drawing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power Supply | 5 V ±10% main supply for core logic, Flash, SRAM, and I/Os |
| GND | Ground Reference | Common return path for all analog/digital functions; requires low-impedance PCB plane |
| A0–A15 | Address Inputs | 16-bit address bus interface to 8-bit MCU; supports multiplexed/non-multiplexed configurations |
| D0–D7 | Data Bus | 8-bit bidirectional data path shared with MCU; latched during WRITE/READ cycles |
| RD, WR, CS, OE | Control Signals | Standard 8-bit bus strobes; configurable for 80C51, 80C251, or 68HC11 timing protocols |
| TCK, TMS, TDI, TDO | JTAG ISP Interface | IEEE 1149.1-compliant boundary-scan port on Port E; enables full-chip programming and debug |
| PAGE0–PAGE7 | Page Register Outputs | 8-bit page address extension; multiplies effective MCU address space by 256× (0–255 pages) |
| PE0–PE7 | Port E I/O Pins | Configurable as JTAG signals, general I/O, or PLD inputs; dedicated TCK/TMS/TDI/TDO mapping |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank Flash architecture | Enables real-time firmware updates: read active code from Bank A while reprogramming Bank B |
| Reconfigurable PLD subsystem | Combines fixed CPLD (16 OMCs) and user-defined DPLD for custom chip select logic without external glue logic |
| 52-pin I/O flexibility | Each pin supports MCU I/O, PLD I/O, latched address output, or special function roles - reducing board complexity |
| JTAG-based ISP | Eliminates need for UV erasers or socket programming; supports manufacturing test and field firmware upgrades |
| Page register addressing | Extends 16-bit MCU address bus to 24-bit space (64 MB), enabling seamless integration with legacy 8-bit cores |
| Low-power standby mode | 50 µA typical current draw in APD mode; ideal for battery-backed industrial controllers and metering devices |
Applications
| Industrial PLC I/O Expansion | Legacy MCU-Based HMI |
|---|---|
Use Scenario: Adding isolated digital I/O, analog monitoring, and local firmware storage to DIN-rail mounted PLC modules. IC Role / Device Role / Timing Role: Acts as unified memory + logic + interface hub between 80C51 controller and peripheral ASICs/sensors. Use Value: Replaces discrete Flash, SRAM, CPLD, and address decoder ICs - reducing BOM count and PCB area by >40%. |
Use Scenario: Upgrading aging factory-floor HMIs based on 80C251 microcontrollers with secure, field-upgradable firmware. IC Role / Device Role / Timing Role: Provides dual-bank Flash for A/B firmware images and PLD-based display controller interface logic. Use Value: Enables zero-downtime firmware patching via JTAG; eliminates need for service technician onsite reprogramming. |
| Automotive Body Control Module | Medical Diagnostic Equipment |
Use Scenario: Implementing door lock, lighting, and window control logic in cost-sensitive 12 V automotive modules. IC Role / Device Role / Timing Role: Integrates program memory, data RAM, and CAN/LIN interface glue logic for 8-bit MCU host. Use Value: Meets AEC-Q100 Class 3 temp range (−40°C to +85°C) and supports 5 V supply directly from vehicle battery rail. |
Use Scenario: Supporting boot firmware, calibration data storage, and sensor interface logic in portable diagnostic tools. IC Role / Device Role / Timing Role: Hosts secure bootloader in protected Flash sector and stores calibrated ADC coefficients in SRAM. Use Value: 15-year data retention and 100,000 Flash endurance ensure long-term accuracy compliance for FDA-regulated devices. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable system device applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD813F2-90UI | Smaller memory: 2 Mbit + 128 Kbit Flash, 32 Kbit SRAM; same PLD structure and pinout | Suitable for less complex 8-bit systems with lower code/data footprint | Select when design fits within halved memory capacity and requires identical PLD/JTAG features |
| PSD834G2-90UI | Same 4 Mbit + 256 Kbit Flash and 64 Kbit SRAM, but lacks DPLD block and has reduced PLD gate count (~2000 gates) | Applicable where only CPLD-based decoding is needed, not user-defined chip selects | Choose when PLD logic requirements are limited to fixed output macrocells and no DPLD configuration is required |
Compared with PSD813F2-90UI and PSD834G2-90UI, the PSD835G2-90UI uniquely delivers full dual-bank Flash concurrency *plus* both CPLD and DPLD blocks - making it the only option among the three supporting fully customizable internal chip select decoding alongside real-time firmware swapping.
Availability
PSD835G2-90UI is available at Aetrix Electronics and suitable for industrial PLCs, legacy MCU-based HMIs, automotive body control modules, and medical diagnostic equipment requiring stable component supply across extended product lifecycles.
Supply support for PSD835G2-90UI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and programmable logic devices for industrial, automotive, and consumer markets.
The PSD (Programmable System Device) product line was developed to consolidate Flash memory, SRAM, and PLD logic into a single chip for 8-bit MCU systems - reducing board complexity, improving reliability, and accelerating time-to-market for legacy architecture upgrades.
FAQ
Is PSD835G2-90UI still in production?
No - PSD835G2-90UI is marked as Obsolete by STMicroelectronics per its official documentation. However, Aetrix Electronics maintains verified legacy inventory with full traceability, including original ST packaging, date codes, and RoHS compliance documentation for continued support of existing designs.
What development tools are required for programming?
PSDsoft™ software (v3.x or later) and a FlashLINK JTAG programming cable are required. PSDsoft provides graphical PLD configuration, Flash memory partitioning, page register setup, and JTAG boundary-scan testing - all validated against ST's official reference designs and timing models.
Can it interface directly with an 8051 without external logic?
Yes - the PSD835G2-90UI supports native 80C51 bus timing (including ALE, PSEN, RD, WR) in both multiplexed and non-multiplexed modes. Its built-in page register and PLD eliminate the need for external address latches or decode PALs in standard 8051-based systems.
Does it support in-application programming (IAP)?
Yes - the dual-bank Flash architecture enables true IAP: the MCU can execute code from one Flash bank while reprogramming the other. This requires proper sector protection configuration and use of the PSD's internal command register sequence, documented in Section 8 of the datasheet.
PSD835G2-90UI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 80-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 80-LQFP (12x12)
- Grade:
- -
- Qualification:
- -
PSD835G2-90UI FAQ
1.How can I place an order for PSD835G2-90UI through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD835G2-90UI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD835G2-90UI reliable?
The price and inventory of PSD835G2-90UI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD835G2-90UI is usually 5 days.
3.What payment methods are accepted for PSD835G2-90UI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD835G2-90UI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD835G2-90UI?
PSD835G2-90UI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD835G2-90UI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD835G2-90UI?
For technical support, including PSD835G2-90UI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD835G2-90UI requirements.
6.How does Aetrix verify that PSD835G2-90UI is sourced from the original manufacturer or authorized distributors?
All PSD835G2-90UI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD835G2-90UI meets industry standards.
7.What is the process for return or replacement of PSD835G2-90UI?
All PSD835G2-90UI units undergo pre-shipment inspection (PSI). If there is an issue with PSD835G2-90UI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD835G2-90UI part is unused and in its original packaging.
Return procedure for PSD835G2-90UI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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