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STMicroelectronics PSD835G2V-12UI
- Part No.:
- PSD835G2V-12UI
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 80-LQFP
- Datasheet:
-
PSD835G2V-12UI.pdf
- Description:
- IC PROG PERIPH IC 80LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:4,697
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Product details
Overview
PSD835G2V-12UI from STMicroelectronics is a programmable system device (PSD) integrating dual Flash memory (4 Mbit primary + 256 Kbit secondary), 64 Kbit SRAM, CPLD/DPLD logic (3000+ gates), and 52 reconfigurable I/O ports for 8-bit microcontroller systems. It supports concurrent read/erase/write operations, in-system programming via JTAG, and page register–based address expansion. Used in legacy industrial controllers requiring embedded nonvolatile storage and glue logic consolidation.
For engineers reviewing the PSD835G2V-12UI datasheet, PSD835G2V-12UI pinout, PSD835G2V-12UI application, or PSD835G2V-12UI equivalent, key selection criteria include Flash bank concurrency, JTAG ISP capability, PLD macrocell count, 3 V supply operation, and LQFP80 package compatibility with 8-bit MCU buses (e.g., 80C51XA, 68HC11).
Technical Context
The PSD835G2V implements a unified architecture where Flash memory banks operate independently-enabling simultaneous READ from one bank while erasing/writing the other. Its PLD subsystem comprises two distinct blocks: a 16-output-macrocell CPLD for combinatorial/synchronous logic and a user-configurable DPLD for chip-select decoding.
Memory access is managed through dedicated control signals (CE, OE, WE), sector protection registers, and a 8-bit page register that extends the MCU's address space by 256×. The JTAG port provides full boundary-scan testing and in-system programming without requiring external high-voltage sources.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Flash Memory | 4 Mbit primary + 256 Kbit secondary; enables concurrent execution and firmware update without halting MCU operation |
| SRAM | 64 Kbit; provides fast, volatile data storage directly accessible via MCU bus with 90 ns access time at 3.3 V |
| PLD Capacity | 3000+ equivalent gates; includes 16 OMCs and 24 IMCs for custom address decoding and peripheral interface logic |
| Supply Voltage | 3.0 V ±10%; supports single-rail operation in battery-backed or low-power industrial systems |
| Standby Current | 25 µA; enables ultra-low-power sleep modes in portable or energy-constrained embedded devices |
| Access Time | 90 ns (VCC = 3.0–3.6 V); ensures timing compatibility with 8-bit MCUs running up to ~11 MHz bus clocks |
| JTAG Interface | Fully compliant IEEE 1149.1; allows production programming, debug visibility, and field firmware updates without socket removal |
Pinout & Package
LQFP80 (U) package per ECOPACK® specification; 80-pin quad flat pack with 0.5 mm pitch, lead-free finish, and thermal pad for enhanced power dissipation in industrial ambient conditions.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC, VSS | Power supply / Ground | Dual power domains: core logic (VCC) and I/O (VCCIO) share same 3 V rail; decoupling required per datasheet layout guidelines |
| CE, OE, WE | Chip Enable / Output Enable / Write Enable | Standard asynchronous memory control signals; support multiplexed and non-multiplexed 8-bit MCU buses (e.g., 80C31, 68HC11) |
| PE4 (Ready/Busy) | Program/Erase status flag | Indicates Flash operation completion or suspension; used for polling-based firmware update synchronization |
| TCK, TMS, TDI, TDO | JTAG test clock / mode select / data in / data out | IEEE 1149.1-compliant boundary-scan chain; enables in-circuit programming and structural testing without external hardware adapters |
| A0–A15, D0–D7 | Address / Data bus | 16-bit address + 8-bit bidirectional data interface; compatible with standard 8-bit microcontrollers using external address latching |
Key Features
| Feature | Design Value |
|---|---|
| Concurrent Flash operation | Enables real-time firmware updates: read active code from primary bank while reprogramming secondary bank |
| Page register addressing | Expands 16-bit MCU address space to 24-bit (64 KB × 256 pages), eliminating need for external address multiplexers |
| Reconfigurable I/O ports | All 52 pins support dynamic mode switching between MCU I/O, PLD I/O, latched address output, or special function roles |
| PLD macrocell flexibility | CPLD offers synchronous/asynchronous clocking per macrocell; DPLD supports user-defined chip-select decoding for multi-peripheral systems |
| Programmable power management | Automatic Power-down (APD) unit reduces current to 25 µA during idle cycles; configurable wake-up triggers via external signals |
Applications
| Industrial PLC I/O Module | Legacy Medical Device Controller |
|---|---|
Use Scenario: Compact programmable logic controller with integrated firmware storage and sensor/actuator interface logic. IC Role / Device Role / Timing Role: Replaces discrete EPROM, SRAM, and PALs; manages address decoding, memory mapping, and real-time I/O state capture. Use Value: Reduces BOM count by consolidating nonvolatile memory, RAM, and glue logic into single LQFP80 device with JTAG field-upgradability. |
Use Scenario: Battery-powered patient monitor requiring long-term firmware retention and low standby power. IC Role / Device Role / Timing Role: Stores boot code and calibration tables in Flash; buffers sensor readings in SRAM; handles interrupt-driven peripheral handshaking. Use Value: 15-year data retention and 25 µA standby current extend battery life while enabling secure in-field firmware patches via JTAG. |
| Automotive Body Control Unit | Test Equipment Firmware Loader |
Use Scenario: Dashboard cluster controller interfacing with CAN transceivers, EEPROM, and display drivers. IC Role / Device Role / Timing Role: Provides memory-mapped configuration space for display fonts and lighting profiles; decodes chip selects for multiple peripherals. Use Value: Dual Flash banks allow A/B firmware partitioning-critical for fail-safe OTA updates without runtime interruption. |
Use Scenario: Automated test fixture that loads firmware images into DUTs before functional validation. IC Role / Device Role / Timing Role: Acts as intelligent memory bridge: receives HEX files over RS-232, verifies checksums, and programs target Flash via parallel bus. Use Value: In-system programming eliminates need for UV erasers or gang programmers-reducing test floor footprint and setup time. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar programmable system device applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD813F2V-12UI | Smaller memory: 2 Mbit primary Flash + 128 Kbit secondary Flash; same PLD architecture and pinout | Suitable for cost-sensitive designs with reduced firmware footprint and fewer peripherals | Select when total memory requirement is ≤2.128 Mbit and BOM cost optimization is prioritized over future scalability |
| PSD834F2V-12UI | Same 4 Mbit + 256 Kbit Flash but lacks DPLD block; only CPLD with 16 OMCs | Cannot implement custom internal chip-select decoding-requires external logic for multi-peripheral systems | Choose only if PLD usage is limited to I/O conditioning and timing logic, not address-space partitioning |
Compared with PSD835G2V-12UI, PSD813F2V-12UI trades memory capacity for lower unit cost, while PSD834F2V-12UI sacrifices DPLD flexibility to simplify logic design-neither matches the full feature set for complex, memory-intensive 8-bit MCU upgrades.
Availability
PSD835G2V-12UI is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy medical device controllers, automotive body control units, and test equipment firmware loaders requiring stable component supply across extended product lifecycles.
Supply support for PSD835G2V-12UI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for automotive, industrial, and consumer markets.
The PSD (Programmable System Device) family was developed to replace discrete memory and logic components in 8-bit microcontroller systems-integrating Flash, SRAM, and PLD resources into a single, JTAG-programmable package for legacy platform modernization.
FAQ
Is PSD835G2V-12UI still in production?
No-PSD835G2V-12UI is marked obsolete by STMicroelectronics (Doc ID 10585 Rev 3, May 2009). However, Aetrix Electronics maintains legacy inventory with full traceability and offers lifecycle support including obsolescence forecasting, cross-reference guidance, and last-time-buy coordination for ongoing production programs.
What development tools are required for programming?
PSDsoft™ software (v3.x or later) is mandatory for configuring PLD logic, generating Flash programming files, and setting memory protection bits. Programming requires a FlashLINK JTAG cable connected to a Windows PC-no external voltage generators or socket adapters are needed due to on-chip charge pumps supporting 3 V ISP.
Can it interface directly with an 8051 microcontroller?
Yes-PSD835G2V-12UI supports both multiplexed (ALE-based) and non-multiplexed 8051 buses. Section 16.6 of the datasheet details timing alignment with 80C51XA derivatives, including wait-state insertion, address latching, and control signal polarity matching for seamless integration without glue logic.
What is the maximum operating temperature range?
The PSD835G2V-12UI is rated for industrial temperature operation from –40 °C to +85 °C, verified per STMicroelectronics' DC and AC parameter testing (Table 31, Doc ID 10585 Rev 3). Thermal derating is not required within this range when mounted on PCBs meeting recommended copper pour and via guidelines.
PSD835G2V-12UI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 80-LQFP
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 80-LQFP (12x12)
- Grade:
- -
- Qualification:
- -
PSD835G2V-12UI FAQ
1.How can I place an order for PSD835G2V-12UI through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD835G2V-12UI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD835G2V-12UI reliable?
The price and inventory of PSD835G2V-12UI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD835G2V-12UI is usually 5 days.
3.What payment methods are accepted for PSD835G2V-12UI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD835G2V-12UI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD835G2V-12UI?
PSD835G2V-12UI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD835G2V-12UI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD835G2V-12UI?
For technical support, including PSD835G2V-12UI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD835G2V-12UI requirements.
6.How does Aetrix verify that PSD835G2V-12UI is sourced from the original manufacturer or authorized distributors?
All PSD835G2V-12UI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD835G2V-12UI meets industry standards.
7.What is the process for return or replacement of PSD835G2V-12UI?
All PSD835G2V-12UI units undergo pre-shipment inspection (PSI). If there is an issue with PSD835G2V-12UI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD835G2V-12UI part is unused and in its original packaging.
Return procedure for PSD835G2V-12UI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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