STMicroelectronics PSD853F2-90J

Overview

PSD853F2-90J from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (1.5 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, JTAG ISP interface, and PLD logic (3000+ gates, 16 OMCs/24 IMCs). It serves as a memory expansion and glue-logic replacement in legacy 80C51/80C251/68HC11 systems.

For engineers reviewing the PSD853F2-90J datasheet, PSD853F2-90J pinout, PSD853F2-90J application, or PSD853F2-90J equivalent, key selection criteria include concurrent Flash bank operation, page register–enabled address space expansion, PLD-based chip select decoding, and JTAG-programmable power management for embedded MCU co-processor roles.

Technical Context

This device implements a unified architecture combining nonvolatile memory, volatile memory, and configurable logic to replace discrete glue logic and external memory in 8-bit MCU designs. Its dual-bank Flash enables background erase/write while executing code from the other bank, and its page register extends the MCU's 16-bit address space by 8-bit page selection (256× expansion).

The integrated PLD comprises two independent blocks: a Decode PLD (DPLD) for user-defined chip select generation and a Complex PLD (CPLD) with 16 output macrocells supporting combinatorial or registered outputs. All 27 I/O pins are individually configurable as MCU data/address lines, PLD I/Os, latched address outputs, or special-function signals-including 16 open-drain capable pins for bus arbitration or wired-OR interfaces.

Key Specifications

Pinout & Package

PSD853F2-90J is housed in a 52-pin PLCC (Plastic Leaded Chip Carrier) package, RoHS-compliant and ECOPACK® certified. Pin assignments follow STMicroelectronics' PLCC52 layout per Appendix B of Doc ID 7833 Rev 7.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Flash+PLD+SRAM peripheral applications.

Compared with PSD854F2-90J, the PSD853F2-90J trades 0.5 Mbit Flash for lower cost and power, while retaining full PLD functionality and concurrent operation; versus PSD833F2-90J, it adds secondary Flash for robust boot code separation and field update resilience.

Availability

PSD853F2-90J is available at Aetrix Electronics and suitable for industrial control panel retrofits, legacy automotive ECU upgrades, and medical data logger enhancements requiring stable component supply and long-lifecycle support.

Supply support for PSD853F2-90J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management, and memory solutions for industrial, automotive, and consumer markets.

The PSD8XXFX product line was developed specifically to extend the lifespan of 8-bit MCU platforms by integrating Flash, SRAM, and PLD logic into a single programmable peripheral-targeting design reuse in cost-constrained, long-lifecycle embedded systems.

FAQ

Is PSD853F2-90J still in production?

No-PSD853F2-90J is marked obsolete by STMicroelectronics (Doc ID 7833 Rev 7, Table 1). However, Aetrix Electronics maintains verified, traceable inventory from authorized legacy channels with full lot traceability and extended warranty coverage for ongoing production and repair programs.

What MCU families does PSD853F2-90J directly interface with?

It natively supports 80C51, 80C251, 80C51XA, and 68HC11 families via dedicated timing and control signal mappings documented in Sections 15.5–15.8 of the datasheet. Interface modes include multiplexed and non-multiplexed buses, with automatic setup via MCU-specific configuration registers.

Can the PLD logic be reprogrammed independently of Flash contents?

Yes-the CPLD and DPLD blocks are programmed separately using JTAG commands defined in Table 6 and Section 19. PLD configuration is stored in Flash but loaded into volatile PLD RAM on power-up; changes to PLD logic do not require erasing Flash code or SRAM data.

Does PSD853F2-90J support 3.3 V operation?

No-it is a 5 V-only device (see Table 40, Operating Conditions). Absolute maximum ratings specify VCC = 4.5 V to 5.5 V; interfacing with 3.3 V MCUs requires level-shifting on address/data/control lines, as confirmed in Section 15 and Table 17.