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STMicroelectronics PSD853F2-90JI
- Part No.:
- PSD853F2-90JI
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 52-LCC (J-Lead)
- Datasheet:
-
PSD853F2-90JI.pdf
- Description:
- IC PROG PERIPH IC 52PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:2,927
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Product details
Overview
PSD853F2-90JI from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (1.5 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, and a 3000-gate PLD with CPLD/DPLD architecture. It supports concurrent read/erase/write operations and features an enhanced JTAG port for in-circuit programming. Used in legacy industrial control systems requiring field-upgradable firmware and configurable logic.
For engineers reviewing the PSD853F2-90JI datasheet, PSD853F2-90JI pinout, PSD853F2-90JI application, or PSD853F2-90JI equivalent, key selection criteria include ISP capability with JTAG, dual-bank Flash concurrency, PLD macrocell count (16 OMCs + 24 IMCs), page register address expansion, and 5 V operation with ECOPACK® PLCC52 packaging.
Technical Context
The PSD853F2-90JI implements a tightly coupled memory-peripheral architecture where the primary Flash (8 × 32K x8 sectors) and secondary Flash (4 × 64K sectors) operate independently-enabling simultaneous execution from one bank while erasing/writing to the other. Its PLD subsystem comprises two distinct blocks: a Decode PLD (DPLD) for user-defined chip select decoding and a Complex PLD (CPLD) with 16 output macrocells supporting synchronous/asynchronous logic.
It interfaces directly with 8-bit MCUs including 80C51XA, 80C251, and 68HC11 via multiplexed or non-multiplexed buses, using dedicated control signals (e.g., RD, WR, CSI) and a programmable page register that extends the MCU's address space by 256×. Power management includes Automatic Power-down (APD) and Turbo Bit mode for dynamic performance scaling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Primary Flash | 1.5 Mbit (8 uniform 32K x8 sectors); enables firmware partitioning and safe over-the-air updates without halting execution. |
| Secondary Flash | 256 Kbit (4 uniform sectors); used for configuration storage, boot code, or data logging independent of main program memory. |
| SRAM | 256 Kbit; provides fast, volatile working memory for MCU stack, buffers, and real-time variables. |
| PLD Capacity | ~3000 gates; integrates glue logic, address decoding, and state machines-reducing external component count. |
| I/O Ports | 27 pins, 16 configurable as open-drain; supports mixed MCU I/O, PLD I/O, latched address outputs, and special functions. |
| Page Register | 8-bit internal register; expands 16-bit MCU address bus to 24-bit effective space (64 KB → 16 MB), enabling large memory mapping. |
| JTAG Interface | IEEE 1149.1-compliant serial port; enables full-chip ISP, boundary-scan testing, and debug access without removing the device. |
Pinout & Package
PSD853F2-90JI is housed in a 52-pin PLCC (Plastic Leaded Chip Carrier) package with J-suffix designation, compliant with ECOPACK® environmental standards. Pin assignments follow STMicroelectronics' PLCC52 layout per Appendix B of Doc ID 7833 Rev 7.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply | +5 V nominal supply for core logic, Flash, SRAM, and I/O; requires local decoupling per datasheet guidelines. |
| GND | Ground reference | Common return path for all digital and analog sections; separate ground planes recommended for noise immunity. |
| A0–A15 | Address inputs | 16-bit address bus interface; supports both multiplexed (AD0–AD7 + A8–A15) and non-multiplexed configurations. |
| D0–D7 | Data bus | 8-bit bidirectional data path; compatible with standard 8-bit MCU data buses (e.g., 80C51, 68HC11). |
| RD, WR, CSI | Control signals | Read strobe, write strobe, and chip select input-enable timing-synchronized memory and PLD access. |
| TCK, TMS, TDI, TDO | JTAG interface | Standard IEEE 1149.1 test access port; used for in-system programming, verification, and boundary-scan diagnostics. |
| PC0–PC7 | Port C I/O | Configurable 8-bit port; JTAG signals are multiplexed on PC0–PC3 when ISP mode is active. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank Flash concurrency | Enables real-time firmware update: MCU executes from Bank A while Bank B is erased and reprogrammed-zero downtime. |
| Reconfigurable PLD architecture | Combines DPLD (custom chip select decoding) and CPLD (16 OMCs/24 IMCs) to replace discrete logic and reduce PCB complexity. |
| 27-pin I/O flexibility | Each pin supports multiple roles (MCU I/O, PLD I/O, latched address, special function); 16 support open-drain for wired-AND bus interfacing. |
| Page register address expansion | Extends 16-bit MCU addressing to 24-bit space (64 KB → 16 MB), eliminating need for external address latches or banking logic. |
| Programmable power management | Includes APD unit, Turbo Bit mode, and PLD-specific power gating-reducing active current by up to 40% in low-utilization states. |
Applications
| Industrial PLC I/O Module | Legacy Medical Device Controller |
|---|---|
Use Scenario: Modular I/O expansion board for programmable logic controllers handling analog/digital sensor inputs and relay outputs. IC Role / Device Role / Timing Role: Acts as memory hub, address decoder, and logic configurator-replacing multiple PALs, EPROMs, and SRAM chips. Use Value: Enables field firmware updates via JTAG without hardware modification; PLD handles custom I/O timing and signal conditioning. |
Use Scenario: Control subsystem in discontinued diagnostic equipment (e.g., ECG analyzers) requiring long-term component availability and reprogrammability. IC Role / Device Role / Timing Role: Provides boot code storage, runtime parameter SRAM, and configurable timing for ADC sampling and display refresh. Use Value: Dual-bank Flash allows safety-critical firmware patches without system reset; page register supports legacy 80C251 address expansion. |
| Automotive Body Control Unit (BCU) | Avionics Maintenance Terminal |
Use Scenario: Centralized lighting, door lock, and window control module in older vehicle platforms with 8-bit MCU architecture. IC Role / Device Role / Timing Role: Integrates non-volatile configuration storage, EEPROM-like parameter retention, and logic for CAN message filtering (via PLD). Use Value: Secondary Flash stores calibration data and fault logs; PLD implements deterministic response timing for safety-critical outputs. |
Use Scenario: Portable maintenance interface for aircraft subsystems (e.g., FDR, CVR) needing secure, field-programmable firmware and hardware abstraction. IC Role / Device Role / Timing Role: Serves as bridge between host processor and legacy avionics peripherals-handling protocol translation and status monitoring. Use Value: JTAG ISP enables certified software updates in hangar environments; SRAM buffers high-speed telemetry streams during diagnostics. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Flash-based programmable peripheral applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD854F2-90JI | Higher primary Flash (2 Mbit vs. 1.5 Mbit); same PLD, SRAM, and pinout. | Better suited for larger firmware images or multi-application partitioning; identical interface and timing. | Select when firmware size exceeds 1.5 Mbit or future scalability is required-no redesign needed. |
| PSD833F2-90JI | Reduced primary Flash (1 Mbit); same secondary Flash, SRAM, PLD, and package. | Targeted at cost-sensitive designs with smaller code footprints; retains full ISP and PLD functionality. | Choose for legacy replacement where existing firmware fits in 1 Mbit and BOM cost reduction is critical. |
Compared with PSD854F2-90JI, the PSD853F2-90JI trades 512 Kbit of primary Flash capacity for tighter cost control while retaining identical PLD resources, SRAM, and ISP capability-making it optimal for mature designs with stable firmware size. Against PSD833F2-90JI, it adds 512 Kbit Flash headroom without altering logic density or power profile.
Availability
PSD853F2-90JI is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy medical device controllers, and automotive body control units requiring stable component supply and long-lifecycle support.
Supply support for PSD853F2-90JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader specializing in microcontrollers, power management, and programmable logic devices for industrial, automotive, and embedded markets.
The PSD8XXFX product line was designed to extend the life of 8-bit MCU platforms by integrating Flash memory, SRAM, and configurable PLD logic into a single ISP-capable peripheral-reducing board space and enabling field upgrades.
FAQ
Is PSD853F2-90JI still in production?
No-PSD853F2-90JI is marked as Obsolete by STMicroelectronics per Doc ID 7833 Rev 7. However, Aetrix Electronics maintains verified legacy inventory with full traceability, conforming to original manufacturing lots and ECOPACK® specifications. We support extended lifecycle requirements through controlled distribution and documentation handover.
What MCU families are natively supported?
The PSD853F2-90JI is validated for direct interface with 80C51XA, 80C251, 80C31, and 68HC11 MCUs. Its bus interface supports both multiplexed (address/data shared) and non-multiplexed configurations, with dedicated timing registers and control signal mapping documented in Sections 15.1–15.8 of the datasheet.
Can the PLD be reprogrammed independently of Flash memory?
Yes-the PLD configuration (CPLD and DPLD) is stored in dedicated non-volatile cells and can be updated separately via JTAG without affecting Flash contents. The JTAG interface supports individual block programming: Flash banks, SRAM initialization, PLD logic, and security registers-all addressable through distinct instruction sequences defined in Table 6 and Section 19.
Does it support 3.3 V operation?
No-PSD853F2-90JI is a 5 V-only device (VCC = 4.5 V to 5.5 V). It is not compatible with 3.3 V I/O systems. STMicroelectronics offered separate 3 V variants (e.g., PSD853F2-90JIT) with different suffixes and DC characteristics; those parts are also obsolete and electrically distinct.
PSD853F2-90JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 52-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 52-PLCC (19.1x19.1)
- Grade:
- -
- Qualification:
- -
PSD853F2-90JI FAQ
1.How can I place an order for PSD853F2-90JI through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD853F2-90JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD853F2-90JI reliable?
The price and inventory of PSD853F2-90JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD853F2-90JI is usually 5 days.
3.What payment methods are accepted for PSD853F2-90JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD853F2-90JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD853F2-90JI?
PSD853F2-90JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD853F2-90JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD853F2-90JI?
For technical support, including PSD853F2-90JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD853F2-90JI requirements.
6.How does Aetrix verify that PSD853F2-90JI is sourced from the original manufacturer or authorized distributors?
All PSD853F2-90JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD853F2-90JI meets industry standards.
7.What is the process for return or replacement of PSD853F2-90JI?
All PSD853F2-90JI units undergo pre-shipment inspection (PSI). If there is an issue with PSD853F2-90JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD853F2-90JI part is unused and in its original packaging.
Return procedure for PSD853F2-90JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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