STMicroelectronics PSD854F2-90J

Overview

PSD854F2-90J from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (2 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, JTAG-based ISP, and a CPLD/DPLD logic block with >3000 gates. It serves as a memory and logic expansion companion for legacy 80C51, 80C251, and 68HC11 MCUs in industrial control and embedded instrumentation.

For engineers reviewing the PSD854F2-90J datasheet, PSD854F2-90J pinout, PSD854F2-90J application, or PSD854F2-90J equivalent, key selection criteria include concurrent Flash bank operation capability, PLD-based chip select decoding, page register address expansion, JTAG ISP support, and 5 V operation with open-drain I/O configuration.

Technical Context

The PSD854F2-90J implements a tightly coupled architecture where MCU bus signals directly drive Flash/SRAM banks and PLD logic blocks via dedicated decode paths. Its dual-bank Flash enables simultaneous read-while-erase/write operations across independent memory spaces, coordinated by internal status flags (DQ3–DQ7) and sector protection registers.

The integrated PLD comprises two distinct units: a 16-output macrocell CPLD for timing-critical glue logic and a user-configurable DPLD for internal chip select generation. Both operate under shared clocking and are programmed via JTAG using the same Flash programming infrastructure.

Key Specifications

Pinout & Package

PSD854F2-90J is housed in a 52-pin PLCC (Plastic Leaded Chip Carrier) package, designated by suffix 'J' per STMicroelectronics part numbering. This surface-mount package features gull-wing leads, 0.5 mm pitch, and is RoHS-compliant and ECOPACK® certified.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Flash+PLD peripheral applications.

Compared with PSD853F2-90J and PSD834F2-90J, the PSD854F2-90J uniquely delivers full dual-bank Flash concurrency, 256 Kbit SRAM, and page register–based address expansion-making it the only option among the three capable of supporting robust, field-upgradable embedded firmware architectures.

Availability

PSD854F2-90J is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, legacy MCU-based test equipment, and automotive ECU diagnostic interface applications requiring stable component supply and long-term obsolescence management.

Supply support for PSD854F2-90J includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, power management ICs, sensors, and analog/mixed-signal devices for industrial, automotive, and consumer markets.

The PSD8XXFX product line was developed specifically to extend the life and capability of 8-bit MCU platforms by integrating Flash memory, SRAM, and programmable logic into a single, JTAG-programmable peripheral-targeting cost-sensitive, long-lifecycle embedded systems.

FAQ

Is PSD854F2-90J still in active production?

No-PSD854F2-90J is marked as Obsolete by STMicroelectronics per Doc ID 7833 Rev 7. However, Aetrix Electronics maintains legacy inventory and offers extended lifecycle support including last-time buy planning, cross-reference assistance, and functional replacements with documented migration paths.

What MCU families does PSD854F2-90J natively support?

PSD854F2-90J provides direct hardware interface support for 80C31, 80C251, 80C51XA, and 68HC11 MCUs, with dedicated timing diagrams and bus interface examples in Sections 15.5–15.8 of the datasheet. It does not support ARM Cortex-M or modern 32-bit cores without external level-shifting or protocol translation.

Can the CPLD and DPLD be programmed independently?

Yes-the CPLD and DPLD logic blocks are programmed separately via JTAG using distinct configuration bitstreams. The DPLD handles internal chip select decoding and address filtering, while the CPLD manages output timing, macrocell state machines, and I/O direction control-each with independent fuse-map allocation.

Does PSD854F2-90J support 3 V operation?

No-PSD854F2-90J is a 5 V-only device per Table 40 (Operating Conditions). It specifies VCC = 4.5 V to 5.5 V and is incompatible with 3.3 V or mixed-voltage I/O systems without level translation. ST's 3 V PSD variants (e.g., PSD854FV) use different part numbering and are not pin- or functionally compatible.