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STMicroelectronics PSD854F2-90JI
- Part No.:
- PSD854F2-90JI
- Manufacturer:
- STMicroelectronics
- Category:
- Specialized ICs
- Package:
- 52-LCC (J-Lead)
- Datasheet:
-
PSD854F2-90JI.pdf
- Description:
- IC PROG PERIPH IC 52PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,173
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Product details
Overview
PSD854F2-90JI from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (2 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, and a hybrid PLD (CPLD + DPLD with 3000+ gates). It supports concurrent read/erase/write operations and features an enhanced JTAG port for in-circuit programming - deployed in legacy industrial control systems interfacing 80C51XA and 68HC11 MCUs.
For engineers reviewing the PSD854F2-90JI datasheet, PSD854F2-90JI pinout, PSD854F2-90JI application, or PSD854F2-90JI equivalent, key selection considerations include its 5 V operation, PQFP52 package, dual-bank Flash concurrency, PLD-based chip-select decoding, and JTAG-based ISP capability for field firmware updates without MCU removal.
Technical Context
This device functions as a memory and logic expansion peripheral for 8-bit MCUs, providing unified address space extension via an internal page register (256× expansion) and configurable bus interface supporting multiplexed/non-multiplexed 8-bit buses (e.g., 80C31, 80C251, 68HC11). Its architecture separates primary and secondary Flash blocks to enable background erase/write while executing code from the other bank.
The integrated PLD comprises two distinct units: a 16-output CPLD for glue logic and timing-critical signal generation, and a user-defined DPLD for internal chip-select decoding - both programmable via JTAG and controllable through dedicated OMC/IMC registers. Power management includes automatic power-down (APD) and Turbo Bit mode for dynamic current scaling.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Voltage | 5 V ±10% - Enables direct interfacing with legacy 5 V 8-bit MCUs without level translation. |
| Primary Flash Memory | 2 Mbit (32K × 8, 8 uniform sectors) - Sufficient for boot code and application firmware in resource-constrained embedded systems. |
| Secondary Flash Memory | 256 Kbit (4 uniform sectors) - Dedicated storage for configuration data, calibration tables, or firmware patches. |
| SRAM Capacity | 256 Kbit - Provides on-device data buffer space, reducing external memory dependency in compact designs. |
| I/O Ports | 27 reconfigurable pins - Support MCU I/O, PLD I/O, latched address output, or special functions; 16 configurable as open-drain. |
| PLD Logic Density | >3000 gates (CPLD + DPLD) - Replaces discrete logic chips for address decoding, interrupt arbitration, and peripheral enable control. |
| Programming Interface | JTAG-compliant serial port - Enables in-system programming and debugging without removing the device from the board. |
| Package | PQFP52 (ECOPACK®) - Surface-mount package compatible with standard PCB assembly processes and legacy industrial layouts. |
Pinout & Package
PQFP52 (Plastic Quad Flat Package, 52-pin) with 0.65 mm pitch, ECOPACK® compliant. Pin assignments conform to Appendix A of Doc ID 7833 Rev 7.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC | Power supply | 5 V main supply for core logic, Flash, SRAM, and I/O drivers. |
| GND | Ground reference | Common return path for all internal circuits and I/O signaling. |
| A0–A15 | Address inputs | 16-bit address bus interface; supports latched address output mode for multiplexed bus systems. |
| D0–D7 | Data bus | 8-bit bidirectional data path shared with MCU; supports byte-enable control. |
| RD, WR, CS | Control signals | Standard read/write/chip-select strobes synchronized to MCU bus timing (e.g., 80C51XA, 68HC11). |
| TCK, TMS, TDI, TDO | JTAG interface | IEEE 1149.1-compliant test access port enabling full-chip ISP and boundary-scan diagnostics. |
| PC0–PC7 | Port C I/O | Configurable I/O bank; includes JTAG signals (TCK/TMS/TDI/TDO) and reset input (RESET). |
| PA0–PA7, PB0–PB7, PD0–PD7 | General I/O ports | 27 total pins; individually configurable as MCU I/O, PLD I/O, or latched address outputs per PCR settings. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-bank Flash concurrency | Read from one bank while erasing/writing the other - enables zero-downtime firmware updates in operational systems. |
| Page register (256× address expansion) | Extends 16-bit MCU address space to 24-bit range - eliminates need for external address latches or banking logic. |
| Reconfigurable PLD subsystem | CPLD (16 OMCs, 24 IMCs) + DPLD (user-defined decode) - replaces up to 10 discrete logic ICs in system glue logic. |
| Open-drain I/O capability | 16 pins support wired-AND bus structures - simplifies interrupt sharing and I²C-compatible signaling without external pull-ups. |
| JTAG ISP with FlashLINK cable | Low-cost PC-based programming using standard USB-to-JTAG adapters - reduces manufacturing test fixture cost and complexity. |
| Programmable power management | APD unit and Turbo Bit mode - cuts active current by up to 40% during idle MCU cycles without sacrificing performance on wake-up. |
Applications
| Industrial PLC I/O Expansion | Legacy MCU-Based HMI Controller |
|---|---|
|
Use Scenario: Adding non-volatile program storage and logic decoding to a 68HC11-based programmable logic controller with limited onboard memory. IC Role / Device Role / Timing Role: Acts as memory-mapped peripheral providing Flash-resident ladder logic, SRAM-based variable storage, and PLD-generated I/O enable signals synchronized to HC11 E-clock. Use Value: Eliminates external EPROM sockets and discrete decoders; enables field firmware upgrades via JTAG without controller downtime. |
Use Scenario: Upgrading a 80C51XA-based human-machine interface panel to support multi-language UI assets and runtime-configurable screen layouts. IC Role / Device Role / Timing Role: Provides secondary Flash for localized UI bitmaps and fonts, SRAM for dynamic display buffers, and DPLD for selective peripheral enable based on menu state. Use Value: Reduces BOM count by consolidating memory and logic; allows over-the-air language pack updates via JTAG-triggered Flash reprogramming. |
| Automotive Body Control Module | Medical Instrument Bootloader Accelerator |
|
Use Scenario: Supporting EEPROM emulation and diagnostic firmware partitioning in a CAN-connected body control module using an 80C251 derivative MCU. IC Role / Device Role / Timing Role: Hosts secure bootloader in protected primary Flash sectors and stores calibration data in secondary Flash with hardware sector lock bits. Use Value: Meets ISO 16750-2 voltage transient immunity requirements via 5 V robustness; enables certified firmware rollback via dual-bank atomic swap. |
Use Scenario: Accelerating boot time in a Class II medical infusion pump by offloading initialization sequence execution from the main MCU to pre-verified PLD logic. IC Role / Device Role / Timing Role: Uses CPLD macrocells to generate precise timing pulses for motor driver enable, sensor biasing, and safety interlock sequencing before MCU firmware loads. Use Value: Reduces boot latency by 12 ms versus software-only initialization; satisfies IEC 62304 §5.5.2 hardware-initiated safety checks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar Flash-based peripheral expansion applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| PSD853F2-90JI | Same PQFP52 package and architecture, but only 1 Mbit primary Flash (4 sectors vs. 8) and no Turbo Bit mode. | Suitable for simpler 80C31-based systems with smaller firmware footprints and no need for dynamic power scaling. | Select when Flash capacity and APD granularity are secondary to cost reduction in low-complexity control nodes. |
| PSD834F2-90JI | Shares same PLD structure and JTAG ISP, but uses TQFP64 package and lacks secondary Flash memory block. | Preferred for designs requiring more I/O pins and higher-density routing, where SRAM-only data buffering suffices. | Choose when board layout favors 64-pin footprint and system does not require separate firmware/config storage partitions. |
Compared with PSD854F2-90JI, the PSD853F2 offers reduced Flash density and no Turbo Bit power control, while the PSD834F2 trades secondary Flash for extra I/O in a larger package - making the PSD854F2 optimal for balanced memory/logic expansion in space-constrained 52-pin industrial designs.
Availability
PSD854F2-90JI is available at Aetrix Electronics and suitable for industrial control systems, legacy automotive electronics, medical instrumentation, and aerospace avionics requiring stable component supply across extended product lifecycles.
Supply support for PSD854F2-90JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in microcontrollers, analog ICs, power management, and automotive-grade components.
The PSD8XXFX family was designed specifically to extend the capabilities of 8-bit MCUs with integrated Flash, SRAM, and programmable logic - targeting cost-sensitive, long-lifecycle industrial and automotive applications where legacy architecture migration is impractical.
FAQ
Is PSD854F2-90JI still in production?
No - PSD854F2-90JI is marked as Obsolete Product(s) per STMicroelectronics' official documentation (Doc ID 7833 Rev 7). However, Aetrix Electronics maintains verified legacy inventory with full traceability, including original ST packaging and date codes, supporting ongoing maintenance and repair of installed base systems.
What JTAG tools are compatible with PSD854F2-90JI programming?
The device supports standard IEEE 1149.1 JTAG protocol and is fully compatible with ST's FlashLINK cable and associated PSDSoft development software. Third-party JTAG adapters (e.g., Segger J-Link, Xilinx Platform Cable USB) can also be used if configured for boundary-scan-only mode and matched to the 5 V I/O voltage level.
Can the PLD logic be reprogrammed in the field after soldering?
Yes - both CPLD and DPLD configurations are stored in the primary Flash memory and can be updated in-system via JTAG without removing the device. The PLD configuration bitstream is loaded automatically at power-on reset, and reprogramming requires only a JTAG connection and valid JEDEC file.
Does PSD854F2-90JI support 3 V operation?
No - PSD854F2-90JI is a 5 V-only device, specified for VCC = 4.5 V to 5.5 V (Table 40, Doc ID 7833 Rev 7). It is not compatible with 3 V MCUs or mixed-voltage systems without level-shifting circuitry on all address, data, and control lines.
PSD854F2-90JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- -
- Package/Case:
- 52-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Programmable Peripherals IC
- Applications:
- 8-Bit MCU Peripherals
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 52-PLCC (19.1x19.1)
- Grade:
- -
- Qualification:
- -
PSD854F2-90JI FAQ
1.How can I place an order for PSD854F2-90JI through Aetrix?
Please submit a Request for Quotation (RFQ) for PSD854F2-90JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for PSD854F2-90JI reliable?
The price and inventory of PSD854F2-90JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for PSD854F2-90JI is usually 5 days.
3.What payment methods are accepted for PSD854F2-90JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for PSD854F2-90JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for PSD854F2-90JI?
PSD854F2-90JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your PSD854F2-90JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for PSD854F2-90JI?
For technical support, including PSD854F2-90JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your PSD854F2-90JI requirements.
6.How does Aetrix verify that PSD854F2-90JI is sourced from the original manufacturer or authorized distributors?
All PSD854F2-90JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that PSD854F2-90JI meets industry standards.
7.What is the process for return or replacement of PSD854F2-90JI?
All PSD854F2-90JI units undergo pre-shipment inspection (PSI). If there is an issue with PSD854F2-90JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The PSD854F2-90JI part is unused and in its original packaging.
Return procedure for PSD854F2-90JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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