STMicroelectronics PSD854F2-90M

Overview

PSD854F2-90M from STMicroelectronics is a Flash in-system programmable (ISP) peripheral IC for 8-bit microcontrollers, integrating dual-bank Flash (2 Mbit primary + 256 Kbit secondary), 256 Kbit SRAM, 27 reconfigurable I/O ports, and a 3000-gate PLD with CPLD/DPLD architecture. It supports concurrent read/erase/write operations and features an internal page register enabling 256× address space expansion - deployed in legacy industrial control systems interfacing with 80C51XA and 68HC11 MCUs.

For engineers reviewing the PSD854F2-90M datasheet, PSD854F2-90M pinout, PSD854F2-90M application, or PSD854F2-90M equivalent, key selection considerations include ISP via JTAG, dual-bank Flash concurrency, PLD-based chip select decoding, open-drain I/O configurability, and 5 V operation with Turbo Bit acceleration.

Technical Context

The PSD854F2-90M implements a tightly coupled memory-peripheral architecture where primary Flash (8 × 32K x8 sectors) and secondary Flash (4 × 64K sectors) operate independently under JTAG-controlled ISP. Its PLD subsystem comprises 16 output macrocells (OMCs) and 24 input macrocells (IMCs), supporting user-defined decode logic for chip select generation and address latching.

Memory access is managed through MCU bus interface modes (multiplexed/non-multiplexed), with dedicated signals including Ready/Busy (PC3), Data Byte Enable, and external Chip Select Input (CSI/PD2). Power management includes Automatic Power-down (APD) and Turbo Bit mode, reducing active current while maintaining 90 ns access timing.

Key Specifications

Pinout & Package

PSD854F2-90M is housed in a 52-pin PQFP (Plastic Quad Flat Package) with 0.65 mm pitch, ECOPACK® compliant. Pin assignments follow STMicroelectronics' standard layout for PSD8XXFX series, supporting multiplexed and non-multiplexed 8-bit bus interfaces.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar Flash+PLD+SRAM peripheral applications.

Compared with PSD853F2-90M and PSD834F2-90M, the PSD854F2-90M delivers full 2 Mbit/256 Kbit memory pairing and 90 ns Turbo Bit timing - making it the highest-capacity, lowest-latency option in the PQFP52 PSD8XXFX family for demanding 8-bit MCU expansions.

Availability

PSD854F2-90M is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, legacy automotive ECU bootloader implementation, and medical device firmware hub applications requiring stable component supply across extended product lifecycles.

Supply support for PSD854F2-90M includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing microcontrollers, analog ICs, power management devices, and memory solutions for industrial, automotive, and consumer markets.

The PSD8XXFX product line was engineered specifically to replace discrete memory, logic, and interface components in 8-bit MCU systems - delivering integrated Flash, SRAM, PLD, and ISP capability in a single programmable peripheral IC.

FAQ

Is PSD854F2-90M still in production?

No - PSD854F2-90M is marked as Obsolete Product(s) per STMicroelectronics' Doc ID 7833 Rev 7 (May 2009). Aetrix Electronics maintains legacy inventory and offers lifecycle coordination support, including last-time-buy planning and cross-reference assistance for functional replacements.

What JTAG tools are compatible with PSD854F2-90M ISP?

The PSD854F2-90M supports IEEE 1149.1-compliant JTAG programmers. ST's original FlashLINK cable (with parallel-port PC interface) is documented in Section 4 of Doc ID 7833. Modern USB-JTAG adapters with boundary-scan support (e.g., Segger J-Link with custom SVF scripting) can also be used if configured for 5 V I/O and TAP controller initialization per Section 19.

Can the PLD logic be reprogrammed independently of Flash memory?

Yes - the CPLD and DPLD blocks are programmed separately from Flash memory using distinct JTAG instructions (Table 6, Doc ID 7833). PLD configuration is stored in on-chip non-volatile cells and retains logic definitions across power cycles, independent of Flash content updates.

Does PSD854F2-90M support 3 V operation?

No - PSD854F2-90M is a 5 V-only device (see Table 40, Operating Conditions). It is not rated for 3 V supply; attempting 3 V operation will result in undefined behavior, failed ISP, or incomplete PLD configuration. The 3 V variants (e.g., PSD854F2-90J) use different suffixes and are pin-compatible but electrically distinct.