Diodes Incorporated PT7M3808G50TAEX

Overview

PT7M3808G50TAEX from Diodes Incorporated is a low-quiescent-current, programmable-delay supervisory IC with fixed 4.65 V voltage threshold (VIT), open-drain RESET output, manual reset input (MR), and CT pin for user-configurable delay timing. It monitors power rails in microcontroller-based systems, asserts reset during brownout or startup, and supports 1.7–6.5 V supply operation with 2.8–6.0 µA supply current. Used in industrial controllers and battery-powered IoT nodes requiring reliable power-on reset.

For engineers reviewing the PT7M3808G50TAEX datasheet, PT7M3808G50TAEX pinout, PT7M3808G50TAEX application, or PT7M3808G50TAEX equivalent, key selection criteria include VIT accuracy (±2.5% over temperature), programmable delay range (20 ms to 1.7 s), SOT23-6 package thermal performance, and MR pull-up resistance (90 kΩ typical).

Technical Context

This supervisory IC implements a precision bandgap reference for VIT detection with 2.5% hysteresis and operates across –40°C to +125°C junction temperature. Its open-drain RESET output supports rail-to-rail pull-up voltages up to 7.0 V independent of VDD, enabling interface with higher-voltage logic domains.

The CT pin enables three delay modes: open-circuit (20 ms), resistor-to-VDD (300 ms), or capacitor-to-ground (0.75 ms to 1.7 s). The SENSE input draws only 25 nA at threshold, minimizing loading on monitored rails, while MR features an internal 90 kΩ pull-up for simplified system-level reset control.

Key Specifications

Pinout & Package

SOT23-6 package with exposed thermal pad (Pin 6 = VDD, Pin 1 = RESET, Pin 3 = MR, Pin 4 = CT, Pin 5 = SENSE, Pin 2 = GND); thermal pad must be connected to ground plane for optimal thermal performance and ESD robustness.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar supervisory applications.

Compared with MAX6326TUT46+T and TPS3808G50DBVR, PT7M3808G50TAEX offers unique CT-programmable delay and active-low MR input-critical for systems requiring field-adjustable timing or hardware-initiated resets-while maintaining competitive quiescent current and VIT accuracy.

Availability

PT7M3808G50TAEX is available at Aetrix Electronics and suitable for industrial automation, smart metering, and portable medical diagnostics requiring stable component supply, long-term lifecycle support, and RoHS 3-compliant packaging.

Supply support for PT7M3808G50TAEX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and mixed-signal solutions for power management, signal integrity, and protection applications.

The PT7M3808 series belongs to Diodes' precision supervisory IC product line, designed specifically for reliable power monitoring and reset generation in space-constrained, low-power embedded systems across industrial, computing, and consumer markets.

FAQ

What is the maximum allowable voltage on the RESET pin?

The RESET pin supports voltages up to 7.0 V regardless of VDD level due to its open-drain architecture and internal clamp diode structure. This allows direct interfacing with 5.0 V or 3.3 V logic families even when VDD is 1.8 V, provided the external pull-up resistor is sized appropriately (10 kΩ to 1 MΩ) to limit sink current to ≤5 mA.

Can the CT pin be left floating to achieve the 20 ms delay?

Yes - leaving the CT pin unconnected (open) configures the device for its factory-fixed 20 ms reset delay. This mode requires no external components and is electrically validated per DS43298 Rev 8-2, with guaranteed delay range of 12–28 ms across temperature and voltage.

How does the SENSE pin behave during power-up when VDD rises slowly?

During slow VDD ramp-up (Trise ≥15 µs/V), the internal POR circuit holds RESET asserted until VDD exceeds VPOR (1.0 V min) and remains asserted for tD after SENSE crosses VIT. The 2.5% hysteresis prevents oscillation if VDD stabilizes near VIT, ensuring clean, single-pulse reset generation.

Is the thermal pad (exposed paddle) electrically connected internally?

No - the thermal pad in the SOT23-6 (TA) package is not electrically connected to any internal node. It must be soldered to a PCB ground plane solely for thermal dissipation and mechanical stability; connecting it to any other net may compromise ESD performance and thermal reliability.