NXP Semiconductors PXAS37KBBE,557

Overview

PXAS37KBBE from NXP Semiconductors is a 16-bit OTP-based microcontroller with 32 KB on-chip program memory, 1 KB RAM, and an 8-channel 8-bit A/D converter. It operates from 2.7 V to 5.5 V at up to 30 MHz, supports I²C and dual UARTs, and targets embedded control in industrial instrumentation and sensor interface systems requiring deterministic timing and external memory expansion.

For engineers reviewing the PXAS37KBBE datasheet, PXAS37KBBE pinout, PXAS37KBBE application, or PXAS37KBBE equivalent, key selection criteria include its 80-pin PQFP package, 16 MB addressable space via 24-bit external bus, 10-bit A/D mode capability, and support for power-down wake-up via external interrupt - all critical for resource-constrained, mixed-signal embedded designs.

Technical Context

The PXAS37KBBE implements the XA CPU core with extended architecture features including a 5-channel 16-bit Programmable Counter Array (PCA), three enhanced timers/counters with toggle outputs, and watchdog timer with reset source register (RSTSRC) for cause identification. Its memory subsystem supports internal code execution with external expansion up to 16 MB using configurable 8- or 16-bit data bus width determined by BUSW pin latching at reset.

Peripheral integration includes dual UARTs with independent baud rate generators, I²C master/slave interface sharing pins with A/D channels (P5.6/SCL, P5.7/SDA), and high-impedance programmable I/O ports (P0–P6) supporting quasi-bidirectional, push-pull, open-drain, and input-only modes - enabling flexible signal conditioning and bus interfacing without external logic.

Key Specifications

Pinout & Package

Package: 80-pin LQFP (SOT315-1), 12 × 12 mm body, 0.5 mm pitch, exposed pad not specified.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 16-bit microcontroller applications.

Compared with MB90F387G and HD64F3687F, the PXAS37KBBE offers balanced integration of OTP program storage, 8-channel A/D, dual UARTs, and I²C in a single 80-pin package - making it optimal for cost-sensitive, medium-complexity embedded systems where field updates are unnecessary and analog interface density matters.

Availability

PXAS37KBBE is available at Aetrix Electronics and suitable for industrial data acquisition, smart sensor nodes, legacy equipment interface, and motor control subsystems requiring stable component supply and long-term manufacturability.

Supply support for PXAS37KBBE includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, and IoT applications.

The PXAS37KBBE belongs to the XA-S3 16-bit microcontroller product line, designed specifically for high-performance embedded control in environments demanding robust analog integration, deterministic real-time response, and flexible external memory expansion.

FAQ

What is the maximum operating frequency and voltage range supported by the PXAS37KBBE?

The PXAS37KBBE operates at up to 30 MHz across a supply voltage range of 2.7 V to 5.5 V. This wide voltage window enables direct compatibility with both 3.3 V and 5 V system rails without level-shifting circuitry. The 30 MHz clock is derived from the internal oscillator driven by an external crystal connected to XTAL1/XTAL2, and timing-critical peripherals like the A/D converter and UARTs scale automatically with the CPU clock frequency as documented in the ADCFG and baud rate registers.

Does the PXAS37KBBE support 10-bit A/D conversion, and how is it configured?

Yes, the PXAS37KBBE supports 10-bit A/D conversion by setting the ADRES bit in the ADCON register. In this mode, the upper 8 bits are stored in ADRSHn registers and the two LSBs in ADRSL, requiring sequential reads to avoid data corruption. The ADCFG register must be adjusted to accommodate longer sampling time, and conversion time increases from 4.46 µs (8-bit) to approximately 6.2 µs (10-bit) at 30 MHz. All eight channels (AD0–AD7 on Port 5) remain available in 10-bit mode.

How does the PXAS37KBBE handle external memory interfacing, and what is the role of the BUSW pin?

The PXAS37KBBE supports external memory up to 16 MB using a 24-bit address bus (A0–A23) and configurable 8- or 16-bit data bus width. The BUSW pin (P3.5/T1) is sampled at reset to determine default bus width: low = 8-bit, high = 16-bit. This configures Port 0 (low byte) and Port 2 (high byte) for multiplexed address/data operation. External access timing is controlled via BCR, BTRH, and BTRL registers, and WAIT input (EA/WAIT/VPP) allows dynamic cycle extension for slow memory devices.

Can the PXAS37KBBE generate interrupts from its A/D converter, and how is the source identified?

Yes, the PXAS37KBBE generates A/D conversion complete interrupts when the ADINT flag in ADCON is set and enabled via EAD in IEL and EA in IEL. The interrupt vector is fixed, and priority is set via IPA3 bits 3–0. Crucially, the RSTSRC register does not track A/D events, but the ADINT flag itself - which must be cleared in firmware - serves as the definitive indicator of conversion completion. No hardware auto-clear occurs, preventing missed interrupts in time-critical sampling loops.

What are the power management modes available on the PXAS37KBBE, and how is wake-up implemented?

The PXAS37KBBE supports Idle and Power-down modes controlled via IDL and PD bits in PCON. In Power-down, CPU and most peripherals halt, leaving only the watchdog timer and external interrupt logic active. Wake-up is triggered exclusively by any enabled external interrupt (e.g., INT0, INT1, or PCA edge detection), causing a full reset sequence with RSTOUT assertion and RSTSRC indicating "external reset." No wake-up-from-Power-down via timer or RTC is supported - design must rely on external event signaling.