Renesas QS3384QG
- Part No.:
- QS3384QG
- Manufacturer:
- Renesas
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
QS3384QG.pdf
- Description:
- IC BUS SWITCH 5 X 1:1 24QSOP
- Quantity:
- Payment:

- Shipping:

Inventory:394
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Product details
Overview
QS3384QG from Renesas Electronics is a high-speed CMOS 10-bit bus switch with two independent 5-bit banks, 5 Ω typical ON resistance, zero propagation delay, and industrial temperature support (–40°C to +85°C). It enables bidirectional voltage translation (5V ↔ 3.3V), hot-swap isolation, and clock gating in embedded bus architectures.
For engineers reviewing the QS3384QG datasheet, QS3384QG pinout, QS3384QG application, or QS3384QG equivalent, key selection criteria include bidirectional switch RON, dual enable control logic, undershoot clamp diodes, and QSOP-24 green package compatibility with legacy IDT QuickSwitch® designs.
Technical Context
The QS3384QG implements ten independent N-channel FET switches without inherent body diode to VCC, enabling true bidirectional signal flow and eliminating shoot-through risk. Each switch bank (A0–A4/B0–B4 and A5–A9/B5–B9) is controlled by dedicated BEA and BEB inputs, supporting selective bus segmentation.
It operates at 5 V ±5%, delivers <0.25 ns intrinsic propagation delay (RC-limited), and integrates undershoot clamp diodes on all I/O and control pins-critical for hot-plug resilience and ESD robustness in backplane and docking interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ON Resistance (RON) | 5 Ω typical at VCC = 5 V, VIN = 0 V - ensures minimal signal attenuation and voltage drop across active paths |
| Propagation Delay (tPLH/tPHL) | <0.25 ns max - adds negligible timing overhead in high-speed data buses |
| Input Voltage Range (VIN) | –0.5 V to +7 V - supports overvoltage tolerance and mixed-voltage domain interfacing |
| Switch Isolation (Off-State IOZ) | ±1 μA max - maintains high-impedance integrity during disable, preventing leakage-induced bus contention |
| Operating Temperature | –40°C to +85°C - qualified for industrial-grade embedded systems and docking stations |
| Package | QSOP-24 (Green) - 0.635 mm pitch, surface-mount compatible with automated assembly |
| Capacitance (OFF) | 5–7 pF per channel - minimizes loading on upstream drivers and preserves signal edge rate |
Pinout & Package
QS3384QG is housed in a 24-pin Quarter Size Outline Package (QSOP-24), lead-free and RoHS-compliant ("QG" suffix), with 0.635 mm lead pitch and standard JEDEC MO-137AC footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BEA, BEB | Active-Low Bus Enable Inputs | Independent control of Bank A (A0–A4/B0–B4) and Bank B (A5–A9/B5–B9); LOW enables pass-through |
| A0–A9, B0–B9 | Bidirectional Switch I/O Terminals | Paired channels (A0↔B0, ..., A9↔B9); no directionality-signal flows either way when enabled |
| VCC | Power Supply | 5 V ±5% supply; powers internal logic and switch bias; not connected to signal path |
| GND | Ground Reference | Common return for all switching and control circuitry; critical for noise immunity and clamp diode operation |
Key Features
| Feature | Design Value |
|---|---|
| Zero-propagation-delay switching | RC-limited delay <0.25 ns ensures timing-transparent bus segmentation in >100 MHz systems |
| Undershoot clamp diodes | Integrated clamps on all I/O and control pins protect against –3 V transients during hot-insertion events |
| Dual independent enable control | BEA and BEB allow granular power/performance management-e.g., isolate peripherals while keeping core bus active |
| No intrinsic VCC-to-channel diode | Enhanced N-FET structure prevents unwanted current paths during voltage translation or partial-power-down states |
| 5 Ω low ON resistance | Minimizes insertion loss and maintains signal integrity across 50 Ω–100 Ω transmission lines |
Applications
| Hot-Swappable Docking Station | Voltage-Level Translating Backplane |
|---|---|
Use Scenario: Connecting/removing peripheral modules (e.g., USB, SATA, PCIe add-in cards) while host system remains powered. IC Role / Device Role / Timing Role: Bidirectional bus isolator that blocks fault currents and prevents ground bounce during insertion/removal. Use Value: Enables safe live insertion without system reset; clamping diodes suppress –3 V undershoot spikes observed on hot-plug edges. | Use Scenario: Interfacing 5 V legacy controllers with 3.3 V FPGA I/O banks on a shared backplane. IC Role / Device Role / Timing Role: Passive voltage translator with no level-shifting logic-relies on FET threshold and rail-to-rail conduction. Use Value: Maintains sub-nanosecond timing alignment between domains; 5 Ω RON avoids duty-cycle distortion on high-frequency clocks. |
| Low-Power System Clock Gating | Capacitance-Isolated Test Access Port |
Use Scenario: Dynamically disabling clock distribution to inactive subsystems (e.g., sensors, ADCs) to reduce dynamic power. IC Role / Device Role / Timing Role: Low-latency clock path switch that breaks clock tree continuity without adding jitter or skew. Use Value: Achieves immediate clock stop with <6.5 ns turn-off delay; 7 pF OFF capacitance prevents capacitive loading of upstream clock driver. | Use Scenario: Isolating JTAG or SWD debug ports during functional testing to prevent interference with production firmware execution. IC Role / Device Role / Timing Role: High-isolation bidirectional signal gate placed between debug header and SoC test interface. Use Value: Provides >1 MΩ off-state impedance and ±1 μA leakage-ensures no unintended debug activation or signal coupling during normal operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBT3384CPWR | Same 10-bit dual-bank architecture, 5 V only, TSSOP-24 package; RON = 6 Ω typical | Identical hot-swap and voltage translation use cases; slightly higher RON increases voltage drop at 100 mA loads | Preferred for TI-centric BOMs; requires layout review due to different thermal pad and pin 1 marking |
| 74LVC1G3157GW,125 | Single SPDT analog switch, 1.65–5.5 V supply, SC-70-6; RON = 10 Ω typical | Not scalable to 10-bit; suitable only for point-to-point signal gating-not bus-wide isolation | Only viable for low-pin-count, low-current gating where space is constrained; not a functional replacement |
Compared with SN74CBT3384CPWR and 74LVC1G3157GW,125, the QS3384QG offers the lowest RON and highest channel count in QSOP-24, making it optimal for industrial backplanes requiring simultaneous multi-bit isolation with minimal timing impact.
Availability
QS3384QG is available at Aetrix Electronics and suitable for hot-swappable docking stations, voltage-translating backplanes, and low-power clock-gated embedded systems requiring stable component supply across extended industrial temperature ranges.
Supply support for QS3384QG includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering microcontrollers, analog, power, and connectivity solutions for automotive, industrial, infrastructure, and IoT applications.
The QS3384QG belongs to Renesas' legacy QuickSwitch® bus switch family-designed specifically for zero-delay, bidirectional signal routing in high-reliability industrial and docking systems.
FAQ
What is the maximum allowable undershoot voltage on QS3384QG I/O pins?
The QS3384QG features integrated undershoot clamp diodes rated for –3 V (AC pulse width ≤20 ns) on all switch and control inputs. This protects against transient negative excursions during hot-plug events. Exceeding –3 V risks permanent damage, as absolute maximum rating for VTERM(3) is –0.5 V DC. The QS3384QG must be used within this limit to ensure long-term reliability in docking applications.
Does QS3384QG support 3.3 V-only operation?
No, QS3384QG is specified only for 5 V ±5% operation (4.75 V to 5.25 V). Its VIH minimum is 2.0 V and VIL maximum is 0.8 V, but internal switch biasing and RON performance are characterized exclusively at VCC = 5 V. Using QS3384QG at 3.3 V may result in undefined RON, increased leakage, or failure to meet tPZL/tPLZ specs. For 3.3 V systems, consider Renesas' newer LVC-family alternatives.
Can QS3384QG be used for analog signal switching?
QS3384QG is optimized for digital bus switching-not general-purpose analog signal routing. Its 5 Ω RON and 7 pF OFF capacitance support clean digital edges, but it lacks rail-to-rail input range, guaranteed THD, or bandwidth specs required for audio/RF analog paths. While small-signal analog signals (<10 MHz, <1 VPP) may pass, the QS3384QG datasheet does not characterize or guarantee analog performance. Use dedicated analog switches for such applications.
What is the thermal resistance (θJA) of QS3384QG in QSOP-24 package?
The QS3384QG datasheet does not specify θJA for the QSOP-24 package. Maximum power dissipation is given as 0.5 W at TA = 85°C, implying conservative derating. For thermal design, assume θJA ≈ 120°C/W (typical for green QSOP-24 with minimal copper), and verify junction temperature using PD = I2RON + VCC × ICCD. At full 10-bit toggle @ 100 MHz, total dynamic power remains well below 0.5 W, confirming safe operation without heatsinking.
How does the function table define QS3384QG's enable logic polarity?
The QS3384QG uses active-LOW enable logic: BEA = L and BEB = L connect A0–A4↔B0–B4 and A5–A9↔B5–B9 respectively; any enable HIGH places its bank in high-impedance (Hi-Z). When both BEA and BEB are HIGH, all ten channels are isolated. This polarity simplifies direct connection to open-drain or active-low system control signals. The QS3384QG function table explicitly confirms "H = HIGH, L = LOW, Z = High-Impedance" for all output states.
QS3384QG Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 24-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 5 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-QSOP
QS3384QG FAQ
1.How can I place an order for QS3384QG through Aetrix?
Please submit a Request for Quotation (RFQ) for QS3384QG on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for QS3384QG reliable?
The price and inventory of QS3384QG are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for QS3384QG is usually 5 days.
3.What payment methods are accepted for QS3384QG?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for QS3384QG transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for QS3384QG?
QS3384QG orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your QS3384QG order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for QS3384QG?
For technical support, including QS3384QG datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your QS3384QG requirements.
6.How does Aetrix verify that QS3384QG is sourced from the original manufacturer or authorized distributors?
All QS3384QG products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that QS3384QG meets industry standards.
7.What is the process for return or replacement of QS3384QG?
All QS3384QG units undergo pre-shipment inspection (PSI). If there is an issue with QS3384QG, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The QS3384QG part is unused and in its original packaging.
Return procedure for QS3384QG:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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