Renesas QS3384QG8
- Part No.:
- QS3384QG8
- Manufacturer:
- Renesas
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
QS3384QG8.pdf
- Description:
- IC BUS SWITCH 5 X 1:1 24QSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,741
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
QS3384QG8 from Renesas Electronics is a high-speed CMOS 10-bit bus switch with two independent 5-bit banks, 5 Ω typical ON resistance, zero propagation delay, and industrial temperature support (–40°C to +85°C). It enables bidirectional voltage translation between 5V and 3.3V buses in hot-swap-capable systems.
For engineers reviewing the QS3384QG8 datasheet, QS3384QG8 pinout, QS3384QG8 application, or QS3384QG8 equivalent, key selection factors include its dual-enable control architecture, undershoot clamp diodes on all I/Os, TTL-compatible logic thresholds, and QSOP-24 green package compliance for low-capacitance isolation in power-sensitive digital interfaces.
Technical Context
The QS3384QG8 implements ten independent N-channel FET switches without inherent body diodes to VCC, enabling true bidirectional signal flow with no DC path. Each switch bank (A0–A4/B0–B4 and A5–A9/B5–B9) is controlled by dedicated BEA and BEB inputs, supporting selective bus gating.
It operates at 5V ±5%, delivers pass voltage ≥3.7V at 5V supply, and maintains ≤7 Ω max ON resistance across temperature. Input leakage is ±1 μA, off-state current is ±1 μA, and dynamic supply current is 0.25 mA/MHz - optimized for low-noise, low-power digital interconnects.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ON Resistance | 5 Ω typ. - ensures minimal RC delay and preserves signal integrity in high-speed digital paths |
| Propagation Delay | 0.25 ns max - contributes negligible timing overhead beyond system RC limits |
| Operating Temp | –40°C to +85°C - supports industrial-grade reliability without derating |
| Voltage Translation | 5V ↔ 3.3V - enables level-shifting without external biasing or direction control |
| Input Thresholds | VIH = 2 V min, VIL = 0.8 V max - guarantees compatibility with TTL and CMOS logic families |
| Capacitance (OFF) | 7 pF max per channel - reduces loading on driven and driving sides during isolation |
| Clamp Diodes | Undershoot protection on all I/O and control pins - suppresses negative transients below –0.5 V |
Pinout & Package
QS3384QG8 is housed in a 24-pin QSOP (Quarter Size Outline Package), green RoHS-compliant, with 0.635 mm pitch and standard JEDEC MO-137AC footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BEA | Control Input | Enables A0–A4/B0–B4 bank; active-HIGH, TTL-compatible |
| BEB | Control Input | Enables A5–A9/B5–B9 bank; active-HIGH, TTL-compatible |
| A0–A9 | I/O Terminal | Bus A side of 10 bidirectional switch channels |
| B0–B9 | I/O Terminal | Bus B side of 10 bidirectional switch channels |
| VCC | Power Supply | +5V ±5% supply rail; powers internal logic and switch drivers |
| GND | Ground Reference | Common return for logic and analog paths; critical for noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| No intrinsic diode to VCC | Eliminates unintended conduction paths during voltage mismatch or hot-plug events |
| Zero added ground bounce | Prevents simultaneous switching noise from corrupting adjacent logic or analog circuits |
| Independent dual enable control | Allows selective isolation of two 5-bit data segments without shared timing constraints |
| Clamp diodes on all I/Os | Protects against –3 V AC transients and –0.5 V DC undershoot without external components |
| Low 5 Ω ON resistance | Maintains signal rise/fall times within 10% degradation even at 50 pF load |
Applications
| Hot-Swappable Backplane Interface | Voltage-Translated Memory Subsystem |
|---|---|
Use Scenario: Insertion/removal of PCIe or CompactPCI cards while main system remains powered. IC Role / Device Role / Timing Role: Bidirectional bus switch isolating card-side signals from backplane during insertion sequence. Use Value: Prevents bus contention and latch-up via independent BEA/BEB control while clamping transients from connector arcing. | Use Scenario: Interfacing 3.3V DDR2 SDRAM controller to 5V legacy memory buffer. IC Role / Device Role / Timing Role: Level-translating, capacitance-isolating switch enabling synchronous read/write without direction pins. Use Value: Maintains <0.25 ns added delay and 7 pF OFF-state loading to preserve setup/hold timing margins. |
| Low-Power Clock Gating Block | Isolated Peripheral Expansion Bus |
Use Scenario: Dynamic disabling of clock distribution to inactive MCU peripherals to reduce dynamic power. IC Role / Device Role / Timing Role: High-speed, low-RON gate for 50 MHz system clocks routed to UART/SPI modules. Use Value: Eliminates clock feedthrough and ground bounce during gating transitions, preserving jitter performance. | Use Scenario: Adding isolated USB or CAN controllers to an industrial PLC mainboard via expansion header. IC Role / Device Role / Timing Role: Signal isolation barrier preventing noise coupling between main CPU domain and peripheral domain. Use Value: 5 Ω RON and 7 pF OFF capacitance minimize signal distortion across 10-bit parallel control/data lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBT3384CPWR | Same 10-bit dual-bank architecture, 5 Ω RON, but uses 2.5V–5.5V supply range and lacks undershoot clamps | Requires external TVS for transient protection in hot-swap environments | Preferred when wider VCC range is needed and board-level protection is already implemented |
| 74LVC1G3157GW | Single-channel SPDT switch, 3.7 Ω RON, 1.65V–5.5V operation - not functionally equivalent due to channel count and enable structure | Suitable only for point-to-point isolation, not multi-bit bus segmentation | Use only for low-pin-count, single-signal isolation where dual-enable control is unnecessary |
Compared with SN74CBT3384CPWR and 74LVC1G3157GW, the QS3384QG8 uniquely combines integrated undershoot clamps, strict 5V-only operation for predictable timing, and native dual-bank enable control - making it optimal for industrial hot-swap and voltage-translation applications requiring robustness and deterministic behavior.
Availability
QS3384QG8 is available at Aetrix Electronics and suitable for hot-swapping, voltage translation, and clock gating applications requiring stable component supply, long-term industrial lifecycle support, and RoHS-compliant packaging.
Supply support for QS3384QG8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics Corporation is a global semiconductor leader delivering microcontrollers, analog, power, and connectivity solutions for automotive, industrial, and IoT markets.
The QS3384QG8 belongs to Renesas' QuickSwitch® family of high-speed bus switches, designed specifically for low-latency, low-noise digital interconnects in industrial and telecom infrastructure where signal integrity and hot-plug resilience are critical.
FAQ
What is the maximum operating voltage for QS3384QG8?
The QS3384QG8 supports a supply voltage (VCC) of 5V ±5%, with absolute maximum ratings of –0.5 V to +7 V on all terminals except VCC. Its DC input and switch voltages are rated to +7 V, enabling safe operation with transient overvoltage up to that limit. The device is not rated for continuous operation above 5.25 V, and exceeding this may impact timing or reliability. Always refer to the DC Electrical Characteristics table in the official QS3384QG8 datasheet for validated operating conditions.
Does QS3384QG8 support bidirectional signal flow?
Yes, QS3384QG8 supports fully bidirectional signal flow across all ten channels. Each switch is implemented using an enhanced N-channel FET without an inherent body diode to VCC, eliminating unidirectional conduction paths. This allows signals to pass from A0–A9 to B0–B9 or vice versa with identical ON resistance (5 Ω typ.) and timing characteristics, making it ideal for data bus isolation and voltage translation in either direction.
What package type is used for QS3384QG8?
QS3384QG8 is packaged in a 24-pin QSOP (Quarter Size Outline Package), designated "QG" in the ordering code. It is green (lead-free/RoHS-compliant), has a 0.635 mm lead pitch, and conforms to JEDEC MO-137AC mechanical specifications. This package provides compact footprint and thermal performance suitable for industrial PCB layouts with moderate density and airflow.
How does QS3384QG8 handle undershoot transients?
QS3384QG8 integrates undershoot clamp diodes on all switch (A0–A9, B0–B9) and control (BEA, BEB) inputs, limiting negative excursions to –0.5 V under DC conditions and –3 V for ≤20 ns pulses. This protects internal circuitry during hot-plug events or connector arcing without requiring external diodes. The clamps operate independently per pin and do not affect normal logic operation or ON-resistance performance.
Can QS3384QG8 be used for 5V to 3.3V level translation?
Yes, QS3384QG8 is explicitly qualified for 5V ↔ 3.3V voltage translation. Its TTL-compatible input thresholds (VIH ≥ 2 V, VIL ≤ 0.8 V), 5 Ω ON resistance, and guaranteed pass voltage of 3.7–4.2 V at 5V supply ensure reliable logic-level compatibility. When driven by a 3.3V source into a 5V domain, the switch passes the signal with minimal drop; when driven from 5V into 3.3V, the receiving device sees valid HIGH levels well above its VIH threshold. No external biasing is required.
QS3384QG8 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 24-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 5 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-QSOP
QS3384QG8 FAQ
1.How can I place an order for QS3384QG8 through Aetrix?
Please submit a Request for Quotation (RFQ) for QS3384QG8 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for QS3384QG8 reliable?
The price and inventory of QS3384QG8 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for QS3384QG8 is usually 5 days.
3.What payment methods are accepted for QS3384QG8?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for QS3384QG8 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for QS3384QG8?
QS3384QG8 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your QS3384QG8 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for QS3384QG8?
For technical support, including QS3384QG8 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your QS3384QG8 requirements.
6.How does Aetrix verify that QS3384QG8 is sourced from the original manufacturer or authorized distributors?
All QS3384QG8 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that QS3384QG8 meets industry standards.
7.What is the process for return or replacement of QS3384QG8?
All QS3384QG8 units undergo pre-shipment inspection (PSI). If there is an issue with QS3384QG8, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The QS3384QG8 part is unused and in its original packaging.
Return procedure for QS3384QG8:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
QS3384QG8 Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

