Renesas R5F100BGDNA#U0
- Part No.:
- R5F100BGDNA#U0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
R5F100BGDNA#U0.pdf
- Description:
- IC MCU 16BIT 128KB FLASH 32HWQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,420
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Product details
Overview
R5F100BGDNA#U0 from Renesas is a 32-pin, ultra-low-power 16-bit RL78/G13 microcontroller with 128 KB flash memory, 8 KB data flash, 12 KB RAM, and industrial-grade operation up to +105°C. It integrates a real-time clock, 10-bit ADC (26 channels), UART/SPI/I²C interfaces, 16-bit timers, and operates from 1.6–5.5 V - deployed in battery-powered sensor nodes and industrial control modules.
For engineers reviewing the R5F100BGDNA#U0 datasheet, R5F100BGDNA#U0 pinout, R5F100BGDNA#U0 application, or R5F100BGDNA#U0 equivalent, key selection criteria include its VFBGA-32 package with 0.4-mm pitch, STOP/HALT/SNOOZE low-power modes (0.57 μA RTC+LVD), 41 DMIPS @ 32 MHz, and integrated data flash rewrite capability (1M cycles).
Technical Context
The R5F100BGDNA#U0 implements the RL78 CPU core with CISC architecture and 3-stage pipeline, supporting instruction execution times from 0.03125 μs (32 MHz high-speed mode) to 30.5 μs (32.768 kHz subsystem clock). Its memory subsystem includes 128 KB code flash (1 KB block size), 8 KB background-operable data flash, and 12 KB on-chip RAM.
Peripherals include dual DMA channels, 16-bit timer array (12 channels), real-time clock with calendar/alarm, watchdog timer with dedicated low-speed oscillator, and mixed-signal features: 10-bit ADC with internal 1.45 V reference and temperature sensor, plus configurable I/O ports supporting 1.8/2.5/3.0 V logic interfacing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | RL78 16-bit CISC with 3-stage pipeline, 41 DMIPS @ 32 MHz |
| Flash Memory | 128 KB code flash (1 KB erase blocks); supports self-programming with boot swap |
| Data Flash | 8 KB background operation (BGO); 1,000,000 write cycles; rewrite voltage 1.8–5.5 V |
| RAM | 12 KB on-chip SRAM; used by flash library at start address FF300H |
| Power Modes | HALT (66 μA/MHz), STOP (0.57 μA w/ RTC+LVD), SNOOZE - enables multi-year battery life |
| ADC | 10-bit resolution, 26 input channels, internal 1.45 V reference, integrated temperature sensor |
| Operating Temp | −40°C to +105°C (Industrial G-grade), single 1.6–5.5 V supply |
Pinout & Package
VFBGA-32 package (4 mm × 4 mm, 0.4-mm pitch), RoHS-compliant, moisture sensitivity level 3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P10 | SCK00 / SCL00 | Serial clock for CSI0 or I²C0 master/slave interface |
| P11 | SI00 / RxD0 / TOOLRxD | Serial input for CSI0 or UART0 receive; debug interface input |
| P12 | SO00 / TxD0 / TOOLTxD | Serial output for CSI0 or UART0 transmit; debug interface output |
| P13 | INTP0 / PPG0 | External interrupt 0 input or programmable pulse generator output |
| P14 | INTP1 / PPG1 | External interrupt 1 input or programmable pulse generator output |
| P15 | INTP2 / PPG2 | External interrupt 2 input or programmable pulse generator output |
| P16 | INTP3 / PPG3 | External interrupt 3 input or programmable pulse generator output |
| P17 | INTP4 / PPG4 | External interrupt 4 input or programmable pulse generator output |
| P20 | ANI0 / AVREFP | Analog input 0 or positive reference voltage for ADC |
| P21 | ANI1 / AVREFM | Analog input 1 or negative reference voltage for ADC |
| P22 | ANI2 | Analog input 2 - part of 26-channel 10-bit ADC |
| P23 | ANI3 | Analog input 3 - supports internal temperature sensor readout |
| P30 | CLKP0 / CLKOUT | System clock output or external clock input for main oscillator |
| P31 | CLKP1 / X1 | Crystal oscillator input (high-frequency crystal connection) |
| P32 | X2 | Crystal oscillator output (completes HF crystal circuit) |
| P33 | RTCCLK / SUBCLK | Real-time clock input or subsystem clock source (32.768 kHz) |
| P40 | RESET | Active-low reset input with internal pull-up; accepts external reset signal |
| VDD | Power Supply | Main supply (1.6–5.5 V); powers core, flash, and most peripherals |
| VSS | Ground | Digital ground reference; multiple pins ensure low-impedance return path |
| AVDD | Analog Power | Separate analog supply (1.6–5.5 V) for ADC and reference circuits |
| AVSS | Analog Ground | Dedicated analog ground; isolated from digital ground to reduce noise coupling |
| EXVCC | External Voltage Ref | Optional external reference input for ADC (bypasses internal 1.45 V ref) |
| P00–P07 | General I/O | Bi-directional ports with N-ch open-drain, TTL input, and pull-up options |
| P147 | ANI18 | Analog input channel 18 - extends ADC coverage to 26 channels |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low-power STOP mode | 0.57 μA retention with RTC and LVD active - enables decade-scale battery operation |
| Background data flash rewrite | Execute code from flash while rewriting 8 KB data flash - no runtime interruption |
| Integrated real-time clock | Full calendar (99 years), alarm, and auto-correction - eliminates external RTC IC |
| Multi-voltage I/O interface | Direct 1.8/2.5/3.0 V logic compatibility - simplifies interconnect with modern sensors |
| On-chip debug support | Fully functional on-chip debug via TOOLRxD/TOOLTxD pins - no external debugger required |
| Hardware multiplier/divider | 16×16→32-bit multiply, 32÷32→32-bit divide, MAC - accelerates control algorithms |
Applications
| Smart Utility Metering | Industrial Sensor Node |
|---|---|
|
Use Scenario: Battery-powered gas/water meter with hourly pulse logging, tamper detection, and RF wake-up. IC Role / Device Role / Timing Role: Main system controller managing ADC sampling, RTC timestamping, EEPROM emulation, and low-power RF transceiver interface. Use Value: 0.57 μA STOP mode extends 10-year battery life; integrated data flash replaces external EEPROM for secure event logging. |
Use Scenario: Wireless vibration/temperature node in factory machinery monitoring. IC Role / Device Role / Timing Role: Signal acquisition hub collecting analog sensor data, performing FFT preprocessing, and scheduling BLE transmissions. Use Value: 26-channel 10-bit ADC captures multi-sensor inputs; BGO allows real-time processing during flash-based firmware updates. |
| Home Appliance Control | Medical Wearable Monitor |
|
Use Scenario: Smart washing machine control board requiring motor timing, user interface, and energy metering. IC Role / Device Role / Timing Role: Central MCU coordinating PWM motor drivers, touch UI, current sensing, and display backlight control. Use Value: 16-bit timer array provides precise phase-controlled triac firing; 12 KB RAM accommodates real-time PID control buffers. |
Use Scenario: Portable ECG patch with continuous analog front-end sampling and Bluetooth LE telemetry. IC Role / Device Role / Timing Role: Analog-digital bridge converting raw biopotential signals, applying digital filtering, and managing secure wireless transmission. Use Value: Internal temperature sensor validates ADC reference stability; −40°C to +105°C rating ensures reliability across body-worn thermal profiles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F100BGDSA#V0 | LQFP-32 package (7 × 7 mm, 0.5-mm pitch); same memory/peripheral spec | Requires PCB redesign for larger footprint and different thermal profile | Select when board layout favors exposed-pad QFP for easier rework or thermal management |
| R5F101BGDNA#U0 | No data flash (0 KB); identical core, RAM, ADC, and low-power modes | Not suitable for field firmware updates or secure parameter storage | Choose only if application requires pure code storage without runtime data logging or configuration persistence |
Compared with R5F100BGDNA#U0, the R5F100BGDSA#V0 offers identical functionality in a more serviceable LQFP package but increases board area and assembly cost; the R5F101BGDNA#U0 reduces bill-of-materials cost by removing data flash but eliminates field-upgradable firmware and secure calibration storage capabilities.
Availability
R5F100BGDNA#U0 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart utility meters, and medical wearable monitors requiring stable component supply across extended product lifecycles.
Supply support for R5F100BGDNA#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RL78/G13 family delivers ultra-low-power 16-bit MCUs optimized for cost-sensitive, battery-operated industrial and consumer devices requiring long-term reliability and integrated analog peripherals.
FAQ
What is the maximum operating frequency and corresponding performance of the R5F100BGDNA#U0?
The R5F100BGDNA#U0 achieves a maximum operating frequency of 32 MHz using its high-speed on-chip oscillator, delivering 41 DMIPS of processing performance. Its minimum instruction execution time is 0.03125 μs under this condition, and it supports dynamic clock scaling down to 32.768 kHz for ultra-low-power RTC operation.
Does the R5F100BGDNA#U0 support in-system programming and secure firmware updates?
Yes, the R5F100BGDNA#U0 supports full in-system programming via its on-chip debug interface and includes flash shield window and block erase prohibition features for secure firmware protection. Self-programming with boot swap functionality enables safe dual-bank firmware updates without external programmers.
What are the key low-power modes supported by the R5F100BGDNA#U0 and their typical current consumption?
The R5F100BGDNA#U0 supports HALT (66 μA/MHz), STOP (0.57 μA with RTC and LVD active), and SNOOZE modes. In STOP mode, only the real-time clock and low-voltage detector remain operational, enabling multi-year battery life in intermittent-sensing applications.
Can the R5F100BGDNA#U0 interface directly with 1.8 V or 2.5 V peripheral ICs?
Yes, the R5F100BGDNA#U0 supports different-potential interface operation: its I/O ports can be configured to interface directly with 1.8 V, 2.5 V, or 3.0 V logic devices without level shifters, thanks to independent input threshold control and selectable pull-up resistors.
What is the endurance and voltage range for data flash writes on the R5F100BGDNA#U0?
The R5F100BGDNA#U0 provides 8 KB of data flash rated for 1,000,000 write/erase cycles (typical) and supports rewriting across the full supply range of 1.8 V to 5.5 V - enabling robust parameter storage and field firmware updates even in brown-out conditions.
R5F100BGDNA#U0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 32-WFQFN Exposed Pad
- Series:
- RL78/G13
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 22
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 12K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 8x8/10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F100BGDNA#U0 FAQ
1.How can I place an order for R5F100BGDNA#U0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F100BGDNA#U0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F100BGDNA#U0 reliable?
The price and inventory of R5F100BGDNA#U0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F100BGDNA#U0 is usually 5 days.
3.What payment methods are accepted for R5F100BGDNA#U0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F100BGDNA#U0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F100BGDNA#U0?
R5F100BGDNA#U0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F100BGDNA#U0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F100BGDNA#U0?
For technical support, including R5F100BGDNA#U0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F100BGDNA#U0 requirements.
6.How does Aetrix verify that R5F100BGDNA#U0 is sourced from the original manufacturer or authorized distributors?
All R5F100BGDNA#U0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F100BGDNA#U0 meets industry standards.
7.What is the process for return or replacement of R5F100BGDNA#U0?
All R5F100BGDNA#U0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F100BGDNA#U0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F100BGDNA#U0 part is unused and in its original packaging.
Return procedure for R5F100BGDNA#U0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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