Renesas R5F100GLDNA#U0
- Part No.:
- R5F100GLDNA#U0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
R5F100GLDNA#U0.pdf
- Description:
- IC MCU 16BIT 512KB FLASH 48HWQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F100GLDNA#U0 from Renesas is a 48-pin HWQFN-packaged RL78/G13 16-bit microcontroller with 128 KB flash, 8 KB data flash, and 12 KB RAM, operating from 1.6 V to 5.5 V at up to 32 MHz (41 DMIPS), featuring ultra-low-power modes (0.57 μA RTC+LVD), integrated 10-bit ADC (26 channels), and real-time clock with calendar function - deployed in industrial sensor nodes and battery-powered control modules.
For engineers reviewing the R5F100GLDNA#U0 datasheet, R5F100GLDNA#U0 pinout, R5F100GLDNA#U0 application, or R5F100GLDNA#U0 equivalent, key selection criteria include its industrial-grade temperature range (–40°C to +105°C), on-chip debug support, self-programmable flash with boot swap, and hardware-accelerated multiply-accumulate for motor control firmware.
Technical Context
The R5F100GLDNA#U0 implements the RL78 CPU core with 3-stage pipeline CISC architecture, supporting instruction execution times from 0.03125 μs (32 MHz high-speed mode) to 30.5 μs (32.768 kHz subsystem clock), and features a unified 1 MB address space with four register banks of eight 8-bit registers each.
It integrates dual power management domains: a main domain with HALT/STOP/SNOOZE low-power modes and a dedicated low-speed oscillator for watchdog and RTC operation; memory subsystem includes background operation (BGO) for data flash rewriting while executing code from program memory.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core Architecture | RL78 16-bit CISC with 3-stage pipeline and 1 MB address space |
| Max Operating Frequency | 32 MHz (41 DMIPS), with selectable high-speed on-chip oscillator ±1.0% accuracy |
| Memory Configuration | 128 KB code flash (1 KB block size), 8 KB data flash (1M rewrite cycles), 12 KB RAM |
| Power Consumption | 66 μA/MHz active; 0.57 μA in STOP mode with RTC + LVD enabled |
| Analog Peripherals | 10-bit ADC with 26 input channels, internal 1.45 V reference, and integrated temperature sensor |
| Timer Resources | 16-bit timer × 12 channels, 12-bit interval timer × 1, RTC with calendar/alarm/correction, WDT with dedicated oscillator |
| Serial Interfaces | CSI (SPI-like) × 6, UART/LIN × 4, I²C × 6 - all configurable per channel |
Pinout & Package
Package: 48-pin HWQFN (7 mm × 7 mm, 0.5 mm pitch), exposed thermal pad, RoHS-compliant, rated for industrial temperature range (–40°C to +105°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD, VSS | Power supply and ground | Dual VDD/VSS pairs ensure stable core and I/O rail decoupling; supports 1.6–5.5 V operation |
| P00–P07 | General-purpose I/O port | Configurable as N-ch open-drain (6 V tolerant), TTL input, or pull-up; supports different-potential interface (1.8/2.5/3 V) |
| P10–P17 | Multi-function port group | Shares SCK00/SCL00, SI00/RxD0, SO00/TxD0, and external interrupt capability |
| P20–P27 | Analog input port | Hosts ANI0–ANI7, AVREFP/AVREFM, and temperature sensor input - calibrated for 10-bit precision |
| RESET | Active-low reset input | Accepts external reset; internally tied to on-chip POR and LVD with 14-level voltage detection |
| CLKP/CLKM | Crystal oscillator inputs | Supports external crystal (32.768 kHz or 1–20 MHz); optional use of high-speed on-chip oscillator instead |
Key Features
| Feature | Design Value |
|---|---|
| Self-programmable flash | Enables field firmware updates with boot swap and flash shield window protection against unauthorized access |
| Background operation (BGO) | Allows concurrent code execution from flash while rewriting data flash - critical for logging without system interruption |
| Hardware MAC unit | Performs 16×16+32-bit signed/unsigned multiply-accumulate in single cycle - accelerates PID and filter algorithms |
| Real-time clock (RTC) | Calendar function (99-year range), alarm, and auto-correction via 32.768 kHz crystal - eliminates external RTC IC |
| Low-voltage detection (LVD) | 14 programmable threshold levels with interrupt or reset output - enables graceful shutdown below safe VDD |
| Key interrupt function | Dedicated hardware detects key press/release on any port pin without CPU polling - reduces wake-from-STOP latency |
Applications
| Industrial Sensor Node | Smart HVAC Controller |
|---|---|
Use Scenario: Battery-powered wireless temperature/humidity sensor with LoRaWAN backhaul and local display. IC Role / Device Role / Timing Role: Main system controller managing ADC sampling, RTC-timed data aggregation, SPI-driven display, and UART-based modem interface. Use Value: Ultra-low 0.57 μA STOP current extends 2-AA battery life beyond 5 years; BGO enables seamless firmware updates over-the-air without interrupting sensor logging. |
Use Scenario: Wall-mounted HVAC zone controller with touch interface, fan speed regulation, and communication to building BMS via RS-485. IC Role / Device Role / Timing Role: Central MCU handling capacitive touch sensing, PWM fan control, RS-485 UART, and real-time scheduling of setpoint adjustments. Use Value: Integrated 10-bit ADC with 26 channels reads multiple thermistors and pressure sensors; hardware MAC accelerates PID loop execution at 100 Hz without jitter. |
| Programmable Logic Relay | Industrial Motor Starter |
Use Scenario: DIN-rail mounted relay module with configurable I/O, Modbus RTU, and onboard logic programming via USB. IC Role / Device Role / Timing Role: Primary processor executing ladder logic, managing isolated digital I/O, and hosting Modbus slave stack over UART. Use Value: 128 KB flash stores complex logic programs and configuration; on-chip debug interface enables field diagnostics without JTAG probe. |
Use Scenario: Three-phase motor starter with soft-start, overload monitoring, and status LED indicators in factory automation equipment. IC Role / Device Role / Timing Role: Real-time controller coordinating 6-channel PWM generation, analog current sensing, thermal shutdown, and fault reporting. Use Value: 16-bit timers with dead-time insertion support precise gate drive timing; 1.6–5.5 V operation tolerates brown-out conditions common in industrial power rails. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F101GLDNA#U0 | No data flash memory (0 KB); identical core, peripherals, and package | Suitable where firmware updates are handled externally or infrequently; lower cost where data logging is unnecessary | Select when persistent parameter storage is implemented in external EEPROM or FRAM |
| RA2A1R5F100GLDNA#U0 | ARM Cortex-M23 core, 128 KB flash, 32 KB SRAM, 12-bit ADC, 105°C rating | Higher performance, richer peripheral set (USB, CAN), but larger code footprint and higher power in active mode | Choose for future-proof designs requiring scalable software architecture or mixed-signal + connectivity integration |
Compared with R5F100GLDNA#U0, R5F101GLDNA#U0 removes data flash but retains full functional compatibility for fixed-parameter systems, while RA2A1 offers ARM ecosystem advantages at the cost of increased design complexity and power budget - making R5F100GLDNA#U0 optimal for cost-sensitive, ultra-low-power industrial control where flash-based data retention is essential.
Availability
R5F100GLDNA#U0 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart HVAC controllers, and programmable logic relays requiring stable component supply across extended product lifecycles.
Supply support for R5F100GLDNA#U0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power solutions for automotive, industrial, and IoT markets.
The RL78/G13 family targets cost-sensitive, ultra-low-power general-purpose applications - designed to replace legacy 8-bit MCUs while delivering 16-bit performance, robust peripheral integration, and industrial temperature resilience.
FAQ
What is the maximum operating frequency and corresponding performance of the R5F100GLDNA#U0?
The R5F100GLDNA#U0 operates at up to 32 MHz using its high-accuracy on-chip oscillator (±1.0%), delivering 41 DMIPS. Its RL78 CPU core achieves this with a 3-stage pipeline and supports variable instruction timing - from 0.03125 μs in high-speed mode to 30.5 μs in ultra-low-speed 32.768 kHz mode - enabling flexible trade-offs between performance and power in the R5F100GLDNA#U0.
Does the R5F100GLDNA#U0 support in-system programming and secure firmware updates?
Yes, the R5F100GLDNA#U0 supports full in-system programming via its on-chip debug interface and includes flash shield window functionality to restrict read/write access to designated memory regions. It also implements boot swap capability, allowing validated firmware images to be loaded into inactive flash banks and atomically activated - ensuring robust, secure firmware updates in the R5F100GLDNA#U0.
What analog capabilities does the R5F100GLDNA#U0 provide for sensor interfacing?
The R5F100GLDNA#U0 integrates a 10-bit successive-approximation ADC with up to 26 input channels, internal 1.45 V reference voltage, and an on-die temperature sensor. It supports simultaneous sampling across multiple channels and operates across the full 1.6–5.5 V supply range - enabling direct interfacing with resistive, capacitive, and thermistor-based sensors without external signal conditioning in the R5F100GLDNA#U0.
How does the R5F100GLDNA#U0 manage ultra-low-power operation in battery-powered applications?
The R5F100GLDNA#U0 achieves 0.57 μA in STOP mode with RTC and LVD active, and 66 μA/MHz in active mode - enabled by multiple low-power states (HALT, STOP, SNOOZE), a dedicated low-speed oscillator for RTC/WDT, and automatic peripheral clock gating. Its voltage detector offers 14 programmable thresholds to trigger controlled shutdown before brown-out - extending operational life in battery-powered R5F100GLDNA#U0 deployments.
Is the R5F100GLDNA#U0 pin-compatible with other RL78/G13 variants in the same package?
Yes, the R5F100GLDNA#U0 uses the 48-pin HWQFN package (PWQN0048KB-A) and shares identical pinout with all other RL78/G13 devices in that package variant - including R5F100GKDNA#U0 and R5F101GLDNA#U0. This allows drop-in replacement within the same memory/peripheral configuration tier, provided PCB layout accommodates the exposed thermal pad and decoupling requirements of the R5F100GLDNA#U0.
R5F100GLDNA#U0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 48-WFQFN Exposed Pad
- Series:
- RL78/G13
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 34
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 8K x 8
- RAM Size:
- 32K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 10x8/10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F100GLDNA#U0 FAQ
1.How can I place an order for R5F100GLDNA#U0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F100GLDNA#U0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F100GLDNA#U0 reliable?
The price and inventory of R5F100GLDNA#U0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F100GLDNA#U0 is usually 5 days.
3.What payment methods are accepted for R5F100GLDNA#U0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F100GLDNA#U0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F100GLDNA#U0?
R5F100GLDNA#U0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F100GLDNA#U0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F100GLDNA#U0?
For technical support, including R5F100GLDNA#U0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F100GLDNA#U0 requirements.
6.How does Aetrix verify that R5F100GLDNA#U0 is sourced from the original manufacturer or authorized distributors?
All R5F100GLDNA#U0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F100GLDNA#U0 meets industry standards.
7.What is the process for return or replacement of R5F100GLDNA#U0?
All R5F100GLDNA#U0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F100GLDNA#U0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F100GLDNA#U0 part is unused and in its original packaging.
Return procedure for R5F100GLDNA#U0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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