Renesas R5F104ACDSP#V0
- Part No.:
- R5F104ACDSP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 30-LSSOP (0.240", 6.10mm Width)
- Datasheet:
-
R5F104ACDSP#V0.pdf
- Description:
- IC MCU 16BIT 32KB FLASH 30LSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
R5F104ACDSP#V0 from Renesas is a 36-pin LFQFP-packaged 16-bit RL78/G14 microcontroller with 16 KB flash, 4 KB data flash, and 2.5 KB RAM, operating from 1.6–5.5 V at up to 32 MHz (44 DMIPS), featuring ultra-low-power HALT/STOP/SNOOZE modes (0.60 μA RTC+LVD), integrated 10-bit ADC (16 channels), UART/SPI/I²C interfaces, and real-time clock - deployed in battery-powered industrial sensor nodes and smart metering front-ends.
For engineers reviewing the R5F104ACDSP#V0 datasheet, R5F104ACDSP#V0 pinout, R5F104ACDSP#V0 application, or R5F104ACDSP#V0 equivalent, key selection criteria include its 36-pin LFQFP-0.5 mm pitch package, -40°C to +85°C industrial temperature grade (D suffix), 16 KB code flash with self-programming and security lock, and support for background data flash rewriting at full VDD range (1.8–5.5 V).
Technical Context
The R5F104ACDSP#V0 implements the RL78 CPU core with 3-stage pipeline CISC architecture, supporting instruction execution times from 0.03125 μs (32 MHz high-speed mode) to 30.5 μs (32.768 kHz ultra-low-speed mode). It integrates a programmable Event Link Controller (ELC) enabling direct peripheral-to-peripheral event triggering without CPU intervention.
Its power management includes on-chip POR and 14-level LVD with interrupt/reset selection, while the Data Transfer Controller (DTC) supports normal, repeat, and block transfer modes activated by 19–26 interrupt sources, including chain transfer for efficient memory-to-peripheral streaming.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RL78 16-bit CISC with 3-stage pipeline; enables deterministic real-time control with low gate count and minimal power per instruction. |
| Max Clock Speed | 32 MHz (44 DMIPS); delivers sufficient throughput for sensor fusion and protocol stack execution in compact embedded systems. |
| Flash Memory | 16 KB code flash + 4 KB data flash; supports background operation (BGO), 1M rewrite cycles, and flash shield window for secure firmware updates. |
| RAM | 2.5 KB on-chip RAM; sufficient for RTOS context switching and dual-bank buffering in communication stacks. |
| ADC | 10-bit resolution, 16-channel SAR ADC with internal 1.45 V reference and temperature sensor; enables direct analog sensing without external components. |
| Low-Power Modes | HALT (66 μA/MHz), STOP (0.60 μA with RTC+LVD active); extends battery life in intermittently active monitoring applications. |
| Operating Voltage | 1.6–5.5 V single supply; allows direct interfacing with 1.8 V, 3.3 V, and 5 V peripherals without level shifters. |
| Temp Range | -40°C to +85°C (industrial grade D); validated for deployment in uncontrolled ambient environments like utility meter enclosures. |
Pinout & Package
Package: 36-pin WFLGA (4 × 4 mm, 0.5 mm pitch), moisture sensitivity level (MSL) 3, RoHS-compliant, lead-free.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P121/X1 | Crystal input | Connects to 32.768 kHz tuning-fork crystal for RTC accuracy; requires external load capacitors (12.5 pF typical). |
| P122/X2/EXCLK | Crystal output / external clock input | Drives crystal oscillator circuit or accepts external clock source up to 20 MHz for precise timing control. |
| P137/INTP0 | Interrupt input 0 | Dedicated edge-triggered wake-up pin; used for immediate system resume from STOP mode on external event. |
| P40/TOOL0 | On-chip debug interface | Enables SWD-based programming and real-time debugging without dedicated JTAG header; shares pin with general I/O. |
| REGC | Regulator bypass capacitor | Must be connected to VSS via 0.47–1 μF ceramic capacitor to stabilize internal voltage regulator for analog/RTC stability. |
| VDD / VSS | Power supply / ground | Single 1.6–5.5 V supply; decoupling required within 5 mm of pins using 100 nF + 4.7 μF capacitors for noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Self-programming with boot swap | Enables field firmware updates with zero downtime via dual-bank flash layout and atomic bank switching. |
| Background data flash rewrite | Permits concurrent program execution and non-volatile parameter storage update - critical for logging and calibration retention. |
| Event Link Controller (ELC) | Eliminates CPU polling overhead by routing 19–26 peripheral events directly to target modules (e.g., ADC trigger → DTC start). |
| Real-time clock with calendar | 99-year calendar, alarm, and auto-correction; operates independently in STOP mode using only 0.60 μA current. |
| Peripheral I/O redirection | Allows dynamic remapping of up to 8 peripheral functions (e.g., UART, SPI) to alternate pins via PIOR0/PIOR1 registers. |
| Dual comparator with window mode | Supports battery voltage monitoring and over/under-voltage detection with programmable thresholds and hysteresis. |
Applications
| Smart Utility Metering | Industrial Sensor Node |
|---|---|
Use Scenario: Gas/water meter with pulse counting, pressure/temperature sensing, and RF sub-GHz telemetry. IC Role / Device Role / Timing Role: Main system controller managing sensor acquisition, metrology calculations, secure data logging, and low-duty-cycle wireless transmission. Use Value: 16 KB flash accommodates DLMS/COSEM stack + application logic; 0.60 μA STOP mode extends 10-year battery life; RTC calendar enables time-stamped billing records. |
Use Scenario: Wireless vibration/temperature node in predictive maintenance for factory machinery. IC Role / Device Role / Timing Role: Edge signal processor acquiring ADC samples, performing FFT preprocessing, and scheduling BLE advertisements. Use Value: 10-bit ADC with internal reference eliminates external precision references; ELC triggers ADC→DTC→RAM transfers autonomously, reducing CPU wake-ups by >70%. |
| Home Appliance Control | Medical Wearable Monitor |
Use Scenario: Smart HVAC remote with touch interface, environmental sensing, and IR/RF control. IC Role / Device Role / Timing Role: System-on-chip handling capacitive touch decoding, sensor fusion (temp/humidity), and multi-protocol IR/RF transmission. Use Value: 36-pin WFLGA enables compact PCB layout; 1.6 V minimum VDD supports single-cell Li-ion operation down to end-of-life; on-chip buzzer controller drives alerts without external driver. |
Use Scenario: Portable ECG/SpO₂ patch with analog front-end, motion compensation, and Bluetooth LE connectivity. IC Role / Device Role / Timing Role: Analog-digital hub digitizing biopotential signals, applying digital filtering, and managing secure BLE data streaming. Use Value: Integrated 10-bit ADC with temperature sensor enables on-chip calibration; STOP-mode RTC maintains session timestamps during sleep; 4 KB data flash stores patient history securely. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F104BCDSP#V0 | 32 KB flash, 5.5 KB RAM, same 36-pin WFLGA package and peripheral set. | Required when firmware exceeds 16 KB or additional RAM needed for larger buffers or RTOS heap. | Select if future firmware growth or enhanced data logging is anticipated; pin-compatible with no PCB change. |
| R5F104ADSP#V0 | 32 KB flash, 4 KB RAM, 30-pin LSSOP package (7.62 mm, 0.65 mm pitch), same voltage/temp specs. | Suitable for space-constrained designs where smaller footprint and lower pin count suffice. | Choose for cost-sensitive, lower-I/O-count applications; requires PCB redesign due to different package and pinout. |
Compared with R5F104ACDSP#V0, the R5F104BCDSP#V0 offers scalable code density without altering hardware layout, while the R5F104ADSP#V0 trades pin count and package size for reduced board area - making the former ideal for firmware evolution and the latter for miniaturized consumer devices.
Availability
R5F104ACDSP#V0 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart utility metering, and home appliance control requiring stable component supply across extended production lifecycles.
Supply support for R5F104ACDSP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for automotive, industrial, and IoT markets.
The RL78/G14 product line delivers true low-power 16-bit MCUs optimized for cost-sensitive, battery-operated industrial and consumer applications demanding robust analog integration and long-term supply assurance.
FAQ
What is the maximum operating frequency and corresponding performance of the R5F104ACDSP#V0?
The R5F104ACDSP#V0 operates at up to 32 MHz with a peak performance of 44 DMIPS. Its RL78 CPU core achieves this via a 3-stage pipeline and optimized instruction set, delivering deterministic real-time response for sensor processing and communication protocols without requiring external accelerators or caches.
Does the R5F104ACDSP#V0 support in-system programming and secure firmware updates?
Yes, the R5F104ACDSP#V0 supports full in-system programming via its on-chip debug interface (TOOL0 pin) and includes flash shield window functionality plus block erase prohibition to prevent unauthorized access or modification of protected code regions during field updates.
How many analog input channels does the R5F104ACDSP#V0 ADC support, and what reference options are available?
The R5F104ACDSP#V0 integrates a 10-bit SAR ADC with up to 16 analog input channels. It supports both external reference voltage and an internal 1.45 V reference, enabling accurate measurements without external reference ICs in most industrial sensing applications.
What low-power modes are available on the R5F104ACDSP#V0, and what is the lowest current consumption achievable?
The R5F104ACDSP#V0 offers HALT, STOP, and SNOOZE modes. In STOP mode with only RTC and LVD active, it consumes just 0.60 μA - verified across the full industrial temperature range (-40°C to +85°C) - making it suitable for decade-long battery operation in remote sensors.
Is the R5F104ACDSP#V0 pin-compatible with other RL78/G14 variants in the same package?
Yes, all RL78/G14 devices in the 36-pin WFLGA package - including R5F104ACDSP#V0, R5F104BCDSP#V0, and R5F104CCDSP#V0 - share identical pinouts and electrical characteristics, enabling seamless migration between flash/RAM configurations without PCB revision.
What serial communication interfaces are integrated into the R5F104ACDSP#V0?
The R5F104ACDSP#V0 integrates three UART channels (one with LIN support), up to ten I²C/simplified I²C channels, and three to eight CSI (SPI-compatible) channels - providing flexible connectivity for sensor arrays, displays, EEPROMs, and wireless transceivers in resource-constrained designs.
R5F104ACDSP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 30-LSSOP (0.240", 6.10mm Width)
- Series:
- RL78/G14
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 21
- Program Memory Size:
- 32KB (32K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 4K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 8x8/10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F104ACDSP#V0 FAQ
1.How can I place an order for R5F104ACDSP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F104ACDSP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F104ACDSP#V0 reliable?
The price and inventory of R5F104ACDSP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F104ACDSP#V0 is usually 5 days.
3.What payment methods are accepted for R5F104ACDSP#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F104ACDSP#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F104ACDSP#V0?
R5F104ACDSP#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F104ACDSP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F104ACDSP#V0?
For technical support, including R5F104ACDSP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F104ACDSP#V0 requirements.
6.How does Aetrix verify that R5F104ACDSP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F104ACDSP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F104ACDSP#V0 meets industry standards.
7.What is the process for return or replacement of R5F104ACDSP#V0?
All R5F104ACDSP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F104ACDSP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F104ACDSP#V0 part is unused and in its original packaging.
Return procedure for R5F104ACDSP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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