Renesas R5F104EEGNA#W0
- Part No.:
- R5F104EEGNA#W0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
R5F104EEGNA#W0.pdf
- Description:
- IC MCU 16BIT 64KB FLASH 40HWQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,611
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F104EEGNA#W0 from Renesas is a 40-pin HWQFN-packaged RL78/G14 16-bit microcontroller with 48 KB flash, 5.5 KB RAM, and 4 KB data flash, operating from 1.6–5.5 V at -40°C to +85°C (industrial grade D), delivering 44 DMIPS at 32 MHz for low-power embedded control in sensor nodes and industrial HMI.
For engineers reviewing the R5F104EEGNA#W0 datasheet, R5F104EEGNA#W0 pinout, R5F104EEGNA#W0 application, or R5F104EEGNA#W0 equivalent, key selection criteria include its 66 μA/MHz active current, RTC+LVD ultra-low-power STOP mode (0.60 μA), 10-bit 20-channel ADC, dual UART/LIN support, and hardware DTC/ELC for deterministic real-time peripheral coordination.
Technical Context
The R5F104EEGNA#W0 implements the RL78 CPU core with 3-stage pipeline CISC architecture, supporting instruction execution times from 0.03125 μs (32 MHz) to 30.5 μs (32.768 kHz), plus multiply/divide/accumulate instructions and 1 MB address space. It integrates a configurable high-accuracy ±1.0% on-chip oscillator (1–64 MHz selectable).
Peripheral subsystems include Timer Array Unit (TAU) with up to 8 channels, 12-bit interval timer, calendar RTC with alarm/correction, watchdog timer, and event-driven control via Event Link Controller (ELC) linking 19–26 event sources to peripherals without CPU intervention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RL78 16-bit CISC CPU with 3-stage pipeline and 1 MB address space |
| Max Clock Speed | 32 MHz - delivers 44 DMIPS for real-time control loop execution |
| Flash Memory | 48 KB code flash + 4 KB data flash - supports background rewriting (BGO) and 1M write cycles |
| RAM | 5.5 KB on-chip RAM - sufficient for RTOS stacks, communication buffers, and sensor fusion variables |
| ADC | 10-bit resolution, 20 analog inputs, internal 1.45 V reference and temperature sensor - enables direct thermistor and voltage monitoring |
| Low-Power Modes | HALT (66 μA/MHz), STOP (0.60 μA with RTC+LVD), SNOOZE - extends battery life in intermittent-sensing applications |
| Operating Voltage | 1.6–5.5 V - allows direct interface with 1.8 V, 3.3 V, and 5 V peripherals without level shifters |
| Temp Range | -40°C to +85°C (Industrial D grade) - qualified for factory automation and building control environments |
Pinout & Package
Package: 40-pin HWQFN (6 × 6 mm, 0.5 mm pitch), exposed die pad recommended to be connected to VSS for thermal and EMI performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00 | TxD1 / TI00 / TRGCLKA | Primary UART transmit, timer input, and debug clock - enables serial comms and time-triggered debugging |
| P01 | RxD1 / TO00 / TRGCLKB | Primary UART receive and timer output - supports full-duplex UART with hardware timing capture |
| P10–P17 | CSI/UART/I²C/SCL/SDA/TRDIOx | Multiplexed serial interfaces - configurable per channel for SPI-like CSI, UART, or I²C with flexible pin assignment |
| P20–P27 | ANI0–ANI7 / AVREFP / AVREFM / ANO0 / ANO1 | Analog input group with dedicated reference pins - supports simultaneous multi-channel sampling with external or internal references |
| P30 | INTP3 / RTC1HZ / SCK00 / SCL00 | Real-time clock interrupt output and I²C/SPI clock - provides precise 1 Hz wakeup and synchronous peripheral control |
| P50/P51 | RxD0/TxD0 / SI00/SO00 / TOOLRxD/TOOLTxD | Dedicated debug UART and SPI master - enables in-system programming and trace without consuming main UART resources |
| RESET | Active-low reset input | Asynchronous reset with internal POR and LVD - ensures reliable startup under brown-out conditions |
| REGC | Regulator bypass capacitor terminal | Requires 0.47–1 μF capacitor to VSS - stabilizes internal voltage regulator for noise-immune operation |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low power STOP mode | 0.60 μA with RTC and LVD active - enables years of operation on coin-cell batteries in wireless sensors |
| Data Flash BGO | Background rewriting while executing code - eliminates interrupt latency during firmware updates or logging |
| Event Link Controller (ELC) | Hardware-triggered peripheral chaining without CPU - reduces ISR overhead and jitter in motor control loops |
| Dual UART with LIN support | Two independent UART modules with LIN bus physical layer compliance - simplifies automotive body electronics integration |
| On-chip debug interface | Fully integrated with FINE v2 - enables non-intrusive breakpoints, memory inspection, and real-time variable watch |
| Peripheral I/O redirection | PIOR0/PIOR1 registers remap functions to alternate pins - increases layout flexibility and avoids signal congestion |
Applications
| Industrial Sensor Node | Smart HVAC Controller |
|---|---|
|
Use Scenario: Battery-powered temperature/humidity/CO₂ sensor node transmitting data via UART-to-LoRaWAN gateway. IC Role / Device Role / Timing Role: Main system controller managing ADC sampling, RTC-based wakeup scheduling, and UART packet framing. Use Value: 0.60 μA STOP mode with RTC extends 10-year battery life; 10-bit ADC with internal reference eliminates external precision references. |
Use Scenario: Wall-mounted HVAC thermostat with local display, button interface, and RS-485 Modbus communication. IC Role / Device Role / Timing Role: Central MCU handling touch/key scanning, PWM fan control, and dual UART (Modbus + display interface). Use Value: Dual UART with LIN-capable hardware supports both Modbus RTU and proprietary display protocol; 44 DMIPS handles real-time PID computation. |
| Factory Automation I/O Module | Medical Infusion Pump Controller |
|
Use Scenario: DIN-rail mounted digital I/O expansion module with 8-channel opto-isolated inputs and relay outputs. IC Role / Device Role / Timing Role: Real-time I/O coordinator using DTC for automatic GPIO state capture and ELC-triggered output updates. Use Value: DTC offloads bit-banging from CPU; ELC enables sub-μs response between input edge and output assertion - meets SIL-2 timing requirements. |
Use Scenario: Portable infusion pump requiring precise motor control, safety interlocks, and battery management. IC Role / Device Role / Timing Role: Safety-critical controller running dual-redundant watchdogs, LVD-monitored power path, and calibrated ADC for pressure sensing. Use Value: On-chip LVD with 14-level programmability detects supply sag before motor stall; 10-bit ADC with temperature sensor enables drift compensation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F104EGGNA#W0 | 128 KB flash, 16 KB RAM, same 40-pin HWQFN package and peripheral set | Supports larger firmware images and complex protocols (e.g., BLE stack + USB CDC) | Select when future firmware growth or additional protocol stacks are anticipated |
| R5F104CEGNA#W0 | 32 KB flash, 4 KB RAM, identical low-power features and pinout | Targeted at cost-sensitive, function-limited designs (e.g., single-sensor endpoint) | Choose for minimal BOM cost where 48 KB flash headroom is unnecessary |
Compared with R5F104EEGNA#W0, R5F104EGGNA#W0 provides scalable flash/RAM for evolving firmware complexity, while R5F104CEGNA#W0 reduces cost and power in fixed-function deployments - all retain identical packaging, timing, and peripheral compatibility.
Availability
R5F104EEGNA#W0 is available at Aetrix Electronics and suitable for industrial sensor nodes, smart HVAC controllers, and factory I/O modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant manufacturing.
Supply support for R5F104EEGNA#W0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, and power management solutions for industrial, automotive, and IoT markets.
The RL78/G14 product line delivers true low-power 16-bit MCUs optimized for cost-sensitive, battery-operated, and industrial control applications demanding robust peripheral integration and certified functional safety support.
FAQ
What is the maximum operating frequency and corresponding DMIPS rating for the R5F104EEGNA#W0?
The R5F104EEGNA#W0 operates at up to 32 MHz and delivers 44 DMIPS performance. This benchmark reflects its RL78 CPU core's 3-stage pipeline efficiency and is measured under standard conditions with cache disabled and typical compiler optimization. The R5F104EEGNA#W0 achieves this performance while maintaining 66 μA/MHz active current consumption.
Does the R5F104EEGNA#W0 support background data flash rewriting while executing program code?
Yes, the R5F104EEGNA#W0 supports Background Operation (BGO) for data flash. This allows the CPU to execute instructions from program memory while simultaneously rewriting data flash sectors - critical for over-the-air firmware updates and real-time data logging without interrupting control tasks. The R5F104EEGNA#W0 guarantees 1,000,000 rewrite cycles at VDD = 1.8–5.5 V.
What low-power modes are available on the R5F104EEGNA#W0, and what is the lowest achievable current draw?
The R5F104EEGNA#W0 offers HALT, STOP, and SNOOZE modes. In STOP mode with only RTC and LVD enabled, it draws just 0.60 μA - verified across -40°C to +85°C. This ultra-low quiescent current enables multi-year operation on CR2032 batteries in wireless sensor endpoints, and the R5F104EEGNA#W0 retains full register context and RTC functionality during STOP.
How many UART interfaces does the R5F104EEGNA#W0 include, and do they support LIN bus communication?
The R5F104EEGNA#W0 integrates two independent UART modules (UART0 and UART2), both compliant with LIN 2.2 physical layer specifications. Each supports automatic LIN header detection, checksum generation, and slave node response timing - enabling direct implementation of LIN slave nodes in automotive body electronics or industrial networks without external transceivers.
What is the analog-to-digital converter specification for the R5F104EEGNA#W0, including resolution, channel count, and reference options?
The R5F104EEGNA#W0 features a 10-bit successive-approximation ADC with up to 20 input channels. It supports both external reference voltages (AVREFP/AVREFM pins) and an internal 1.45 V reference. The ADC includes a built-in temperature sensor and operates across the full 1.6–5.5 V supply range, making the R5F104EEGNA#W0 suitable for direct sensor interfacing without external precision references.
R5F104EEGNA#W0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 40-WFQFN Exposed Pad
- Series:
- RL78/G14
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 28
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 5.5K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 5.5V
- Data Converters:
- A/D 9x8/10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F104EEGNA#W0 FAQ
1.How can I place an order for R5F104EEGNA#W0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F104EEGNA#W0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F104EEGNA#W0 reliable?
The price and inventory of R5F104EEGNA#W0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F104EEGNA#W0 is usually 5 days.
3.What payment methods are accepted for R5F104EEGNA#W0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F104EEGNA#W0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F104EEGNA#W0?
R5F104EEGNA#W0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F104EEGNA#W0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F104EEGNA#W0?
For technical support, including R5F104EEGNA#W0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F104EEGNA#W0 requirements.
6.How does Aetrix verify that R5F104EEGNA#W0 is sourced from the original manufacturer or authorized distributors?
All R5F104EEGNA#W0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F104EEGNA#W0 meets industry standards.
7.What is the process for return or replacement of R5F104EEGNA#W0?
All R5F104EEGNA#W0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F104EEGNA#W0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F104EEGNA#W0 part is unused and in its original packaging.
Return procedure for R5F104EEGNA#W0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F104EEGNA#W0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

