Renesas R5F104FEDFP#V0
- Part No.:
- R5F104FEDFP#V0
- Manufacturer:
- Renesas
- Category:
- Microcontrollers
- Package:
- 44-LQFP
- Datasheet:
-
R5F104FEDFP#V0.pdf
- Description:
- IC MCU 16BIT 64KB FLASH 44LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:1,409
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
R5F104FEDFP#V0 from Renesas is a 44-pin LQFP-44, 96 KB flash, 12 KB RAM RL78/G14 16-bit microcontroller operating from 1.6 V to 5.5 V, delivering 44 DMIPS at 32 MHz with ultra-low power consumption (66 μA/MHz active, 0.60 μA RTC+LVD mode), used in battery-powered industrial sensors and smart metering interfaces.
For engineers reviewing the R5F104FEDFP#V0 datasheet, R5F104FEDFP#V0 pinout, R5F104FEDFP#V0 application, or R5F104FEDFP#V0 equivalent, key selection criteria include its 44-pin LQFP package, 96 KB code flash with data flash, integrated 10-bit ADC (20-channel), dual UART/LIN support, and real-time clock with calendar function for time-stamped telemetry and low-power wake-up control.
Technical Context
The R5F104FEDFP#V0 implements the RL78 CPU core with 3-stage pipeline CISC architecture, supporting instruction execution times from 0.03125 μs (32 MHz) to 30.5 μs (32.768 kHz), and includes on-chip debug, self-programming with boot swap, and background operation for data flash rewriting.
It integrates event-driven peripherals including Event Link Controller (ELC) for 19–26 configurable event sources, Data Transfer Controller (DTC) with chain transfer, and multiple serial interfaces: up to 8 CSI channels, 4 UART/LIN channels, and 10 I²C channels - all configurable via peripheral I/O redirection registers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Core | RL78 16-bit CISC CPU with 3-stage pipeline and multiply/divide/accumulate instructions |
| Max Clock Speed | 32 MHz (44 DMIPS), with selectable high-speed on-chip oscillator (±1.0% accuracy) |
| Memory | 96 KB code flash (1 KB block size), 4 KB data flash (1M rewrite cycles), 12 KB RAM |
| Power Consumption | 66 μA/MHz active mode; 0.60 μA in STOP mode with RTC + LVD enabled |
| Analog Peripherals | 10-bit ADC (20 input channels, internal 1.45 V reference, temperature sensor), 2× comparator, 2× 8-bit DAC |
| Serial Interfaces | 4× UART/LIN, 8× CSI (SPI-compatible), 10× I²C/simplified I²C, all with flexible pin remapping |
| Timers & RTC | 12× 16-bit timers (TAU/Timer RJ/RD/RG), 12-bit interval timer, calendar RTC (99-year range, alarm, correction) |
Pinout & Package
Package: 44-pin LQFP (10 × 10 mm, 0.8 mm pitch), lead-free, RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| P00 | TxD1 / TI00 / TRGCLKA | Primary UART1 transmit; timer input; trace clock A; supports different-potential interface (1.8/2.5/3 V) |
| P01 | RxD1 / TO00 / TRGCLKB | Primary UART1 receive; timer output; trace clock B; enables hardware flow control with P00 |
| P10–P17 | CSI1/SCL11/SDA11/TRDIOD1–TRDIOA0 | Dedicated multi-function serial I/O group supporting SPI, I²C, and LIN transceiver modes with ELC-triggered transfers |
| P120 | ANI19 / VCOUT0 | ADC channel 19 input; voltage-controlled oscillator output for frequency modulation or clock monitoring |
| P137 | INTP0 | External interrupt 0 input with programmable edge sensitivity; used for wake-up from STOP/HALT modes |
| P147 | ANI18 / VCOUT1 | ADC channel 18 input; secondary VCO output for dual-clock domain synchronization |
| RESET | Active-low reset input | Asynchronous reset with internal pull-up; accepts external debounced signal or POR/LVD assertion |
| VDD / VSS | Power supply / Ground | Single 1.6–5.5 V supply; REGC capacitor (0.47–1 μF) required between REGC and VSS for regulator stability |
Key Features
| Feature | Design Value |
|---|---|
| SNOOZE mode operation | Permits UART/LIN or ADC activity during low-power sleep without full CPU wake-up, reducing average system current by >40% in polling-based sensing |
| Background data flash rewrite | Enables firmware updates or logging while executing application code from main flash - no interrupt latency penalty or code relocation needed |
| Peripheral I/O redirection | Allows dynamic assignment of serial, timer, and analog functions to alternate pins via PIOR0/PIOR1 registers - eliminates fixed pin conflicts in layout |
| ELC event linking | Direct hardware routing of 19–26 peripheral events (e.g., ADC end-of-conversion → DTC trigger → RAM store) avoids CPU intervention and ISR overhead |
| Real-time clock with calendar | Hardware-managed date/time tracking (YY.MM.DD hh:mm:ss), alarm interrupt, and ±1 ppm correction via 32.768 kHz crystal - no software RTC stack required |
Applications
| Smart Utility Metering | Industrial Sensor Node |
|---|---|
Use Scenario: Battery-powered gas/water meter with hourly pulse counting, temperature compensation, and GPRS upload. IC Role / Device Role / Timing Role: Main controller managing pulse capture (TI00/TI01), 10-bit ADC for thermistor reading, RTC for timestamping, and UART/LIN for modem communication. Use Value: 0.60 μA STOP mode extends 10-year battery life; data flash stores calibration coefficients and usage logs with 1M rewrite endurance. | Use Scenario: Wireless vibration sensor node in predictive maintenance system, sampling at 1 kHz and transmitting FFT results via BLE gateway. IC Role / Device Role / Timing Role: Signal acquisition MCU triggering ADC via ELC-linked timer, computing RMS/FFT in RAM, and buffering data in data flash before UART transmission. Use Value: Background data flash write allows continuous sampling during log commit; SNOOZE mode cuts active current during idle intervals between bursts. |
| Home Appliance Control | Building Automation Panel |
Use Scenario: Washing machine main board requiring motor phase control, water level sensing, and user interface with buzzer feedback. IC Role / Device Role / Timing Role: System orchestrator driving 2× 8-bit DAC for buzzer tone generation, 2× comparator for analog level detection, and PWM-capable TAU timers for triac control. Use Value: On-chip PCLBUZ0/PCLBUZ1 eliminate external tone generators; N-ch open-drain I/O drives 6 V solenoids directly without level shifters. | Use Scenario: HVAC zone controller interfacing with RS-485 Modbus field devices, ambient sensors, and local LCD display. IC Role / Device Role / Timing Role: Protocol bridge MCU handling UART-to-Modbus RTU conversion, 20-channel ADC for temp/humidity/CO₂, and RTC-synchronized schedule execution. Use Value: Dual UART with LIN support enables native Modbus and diagnostics port; 44-pin LQFP provides sufficient GPIO for keypad, display, and sensor headers without expansion. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 16-bit microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| R5F104FGDFP#V0 | 128 KB flash, 16 KB RAM, same 44-pin LQFP package and peripheral set | Supports larger firmware (e.g., embedded web server, OTA update stack) without changing PCB layout | Select when future firmware growth or dual-bank secure boot is required |
| R5F104FEAFP#V0 | 64 KB flash, 5.5 KB RAM, 44-pin LQFP but uses 0.65 mm pitch (FA variant) | Lower memory footprint suits cost-sensitive designs; requires PCB pad revision for pitch compatibility | Choose for legacy LQFP-44 layouts with 0.65 mm pitch or where flash headroom <64 KB suffices |
Compared with R5F104FEDFP#V0, R5F104FGDFP#V0 offers 33% more flash and 33% more RAM in identical packaging for seamless scalability, while R5F104FEAFP#V0 reduces memory and cost but mandates layout adjustment due to pitch difference - making it a functional alternative only with board revision.
Availability
R5F104FEDFP#V0 is available at Aetrix Electronics and suitable for smart metering, industrial sensor nodes, home appliance control, and building automation panels requiring stable component supply across extended product lifecycles.
Supply support for R5F104FEDFP#V0 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Renesas Electronics is a global semiconductor leader specializing in microcontrollers, analog, power, and SoC solutions for industrial, automotive, and IoT markets.
The RL78/G14 product line delivers true low-power 16-bit MCUs optimized for cost-sensitive, battery-operated, and energy-efficient embedded systems requiring rich analog integration and robust peripheral flexibility.
FAQ
What is the maximum operating frequency and associated performance of the R5F104FEDFP#V0?
The R5F104FEDFP#V0 operates at up to 32 MHz using its high-accuracy on-chip oscillator (±1.0%), delivering 44 DMIPS. Its RL78 CPU core achieves minimum instruction execution times of 0.03125 μs at 32 MHz and supports variable-speed operation down to 32.768 kHz for ultra-low-power RTC functions. This enables deterministic real-time response in motor control and sensor polling applications while maintaining sub-μA sleep currents.
Does the R5F104FEDFP#V0 support in-system programming and secure firmware updates?
Yes, the R5F104FEDFP#V0 supports full in-system programming via on-chip debug interface and includes self-programming capabilities with boot swap function and flash shield window protection. It allows secure firmware updates by locking specific flash blocks against erase/write, and background operation enables data logging to data flash while application code executes from program flash - critical for fail-safe over-the-air updates in remote deployments.
How many analog input channels does the R5F104FEDFP#V0 provide, and what ADC resolution is supported?
The R5F104FEDFP#V0 integrates a 10-bit successive-approximation ADC with up to 20 analog input channels (ANI0–ANI19), operating across the full 1.6–5.5 V supply range. It includes an internal 1.45 V reference voltage and on-die temperature sensor, enabling direct thermal compensation in sensor nodes without external components. Channel selection and conversion triggering can be fully controlled via ELC or software for deterministic timing.
What serial communication interfaces are available on the R5F104FEDFP#V0, and how are they configured?
The R5F104FEDFP#V0 provides 4 UART/LIN channels, up to 8 CSI (SPI-compatible) channels, and up to 10 I²C/simplified I²C channels. All interfaces support peripheral I/O redirection via PIOR0/PIOR1 registers, allowing dynamic pin assignment. UARTs include LIN bus physical layer compliance and break detection; CSI modules support master/slave modes with programmable clock polarity/phase; I²C supports standard/fast-mode speeds and slave address masking.
What power-saving modes are implemented in the R5F104FEDFP#V0, and what is the lowest achievable current draw?
The R5F104FEDFP#V0 implements HALT, STOP, and SNOOZE low-power modes. In STOP mode with only RTC and LVD active, it draws just 0.60 μA at VDD = 1.8–5.5 V and TA = –40 to +85°C. SNOOZE mode permits selective peripheral operation (e.g., UART receive, ADC scan) without waking the CPU core, reducing average current in intermittent communication systems. Wake-up from any mode is possible via external interrupt, RTC alarm, or peripheral event routed through ELC.
R5F104FEDFP#V0 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Package/Case:
- 44-LQFP
- Series:
- RL78/G14
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- RL78
- Core Size:
- 16-Bit
- Speed:
- 32MHz
- Connectivity:
- CSI, I2C, LINbus, UART/USART
- Peripherals:
- DMA, LVD, POR, PWM, WDT
- Number of I/O:
- 31
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 5.5K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.6V ~ 5.5V
- Data Converters:
- A/D 10x8/10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
R5F104FEDFP#V0 FAQ
1.How can I place an order for R5F104FEDFP#V0 through Aetrix?
Please submit a Request for Quotation (RFQ) for R5F104FEDFP#V0 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for R5F104FEDFP#V0 reliable?
The price and inventory of R5F104FEDFP#V0 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for R5F104FEDFP#V0 is usually 5 days.
3.What payment methods are accepted for R5F104FEDFP#V0?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for R5F104FEDFP#V0 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for R5F104FEDFP#V0?
R5F104FEDFP#V0 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your R5F104FEDFP#V0 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for R5F104FEDFP#V0?
For technical support, including R5F104FEDFP#V0 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your R5F104FEDFP#V0 requirements.
6.How does Aetrix verify that R5F104FEDFP#V0 is sourced from the original manufacturer or authorized distributors?
All R5F104FEDFP#V0 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that R5F104FEDFP#V0 meets industry standards.
7.What is the process for return or replacement of R5F104FEDFP#V0?
All R5F104FEDFP#V0 units undergo pre-shipment inspection (PSI). If there is an issue with R5F104FEDFP#V0, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The R5F104FEDFP#V0 part is unused and in its original packaging.
Return procedure for R5F104FEDFP#V0:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
R5F104FEDFP#V0 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

